Pretty simple NAND gate question

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Homework Statement



I was looking through some examples in my Digital Logic book and I stumbled across one that gave an answer of x1[itex]\uparrow[/itex](x2[itex]\uparrow[/itex]x2). The answer I got was x2[itex]\uparrow[/itex](x1[itex]\uparrow[/itex]x2).

After making a truth table I'm finding that these are not equal solutions. Unless, I'm doing something wrong.

The Attempt at a Solution



See above. Any help is appreciated.
 
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NascentOxygen said:
Can you write this in words so I can see where NAND comes into it?

The problem asked to turn x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1 into a NAND only circuit. I used decomposition in the last steps to get my answer.
 
DrummingAtom said:
The problem asked to turn x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1 into a NAND only circuit. I used decomposition in the last steps to get my answer.
Can you show the truth table for x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1? I'm not sure the book answer is correct assuming that ↑ means NAND.
 
I got my question answered today in class. Those two solutions are equivalent. Thanks for the help though.
 
According to my book, ↑, is a NAND gate operator.
 
OK, so again I ask what is the truth table for

x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1

and the truth table for

x1↑(x2↑x2)

or

x2↑(x1↑x2)
 
rcgldr said:
OK, so again I ask what is the truth table for

x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1
Yes, that is exclusive NOR.

and the truth table for

x1↑(x2↑x2)

or

x2↑(x1↑x2)

x2 NAND x2 is just NOT x2

x2↑(x1↑x2) evaluates to x2 NAND NOT x1

So expressions in post #1 are NOT identical.
 
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