Question about integrated circuits

[Gulli]

This is an easy one for those familiar with integrated circuits, but it's been bugging me.

Say you build a circuit out of NAND gates, which have two inputs and one output. Doesn't this mean that the circuit as a whole has multiple inputs (or do some of the outputs loop back to the inputs so the circuit as a whole has only one input)? If so, how does feeding a single current (from the wall) into the circuit do anything for the multiple inputs: they'd all get the same input current and this restricts what the gates can do (for example you can't have input A getting zero current and input B getting nonzero current)? So how do you get the inputs to be different?

 

[berkeman]

This is an easy one for those familiar with integrated circuits, but it's been bugging me.

Say you build a circuit out of NAND gates, which have two inputs and one output. Doesn't this mean that the circuit as a whole has multiple inputs (or do some of the outputs loop back to the inputs so the circuit as a whole has only one input)? If so, how does feeding a single current (from the wall) into the circuit do anything for the multiple inputs: they'd all get the same input current and this restricts what the gates can do (for example you can't have input A getting zero current and input B getting nonzero current)? So how do you get the inputs to be different?

The power from the wall is used to power the circuit, not to provide inputs to the logic gates.

One type of logic integrated circuit (IC) is a microcontroller (uC) or micrprocessor (uP):

http://www.howstuffworks.com/microcontroller.htm
http://en.wikipedia.org/wiki/Microcontroller
http://en.wikipedia.org/wiki/Microprocessor

They typically get their inputs from memory (either on the same IC or from off-chip memory), and also from external inputs (like pushbuttons, sensors, etc.). Those inputs are processed and generate outputs back to memory and also to external actuators and displays.

A building block IC would be something like a PAL (programmable array logic), which has general purpose circuitry inside (including gates, flip-flops, and interconnect arrays). PALs are programmed to perform logic functions based on their internal capabilities, and the configuration information that is generated by compiling your logic design. You could configure a PAL to be an up/down binary counter, for example, based on the state of one of its inputs.

http://en.wikipedia.org/wiki/Programmable_Array_Logic

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[Gulli]

Thanks, that's the answer I was looking for. Memory can provide lots of different inputs simultaneously and that answers my question.

 

[pairofstrings]

PALs are programmed to perform logic functions based on their internal capabilities, and the configuration information that is generated by compiling your logic design.

Can you please tell me how exactly the configuration information is generated by compiling the logic design? How is the logic design compiled?

 

[berkeman]

Can you please tell me how exactly the configuration information is generated by compiling the logic design? How is the logic design compiled?

Sure. You would use some design tool for PALs, CPLDs, FPGAs, etc, like Xilinx's ISE:

http://www.xilinx.com/support/download/index.htm

or Quartus from Altera:

https://www.altera.com/download/software/quartus-ii-we

or other design packages. You would typically code your design in HDL, VHDL, or Verilog, and use the software above to compile your design for a specific target PAL/CPLD/FPGA IC.

Here's a sample tutorial showing how to design, compile and load a Xilinx CPLD:

http://www.electro-tech-online.com/...t/39308-cpld-xilinx-programming-tutorial.html

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[pairofstrings]

I want to know, while programming FPGA, PAL or other logic device is it based on our requirements that pins are allotted the input signal?
How do we know which pin gets what signal?

 

[berkeman]

I want to know, while programming FPGA, PAL or other logic device is it based on our requirements that pins are allotted the input signal?
How do we know which pin gets what signal?

That's part of your design. In the coding of the PAL/CPLD/FPGA circuitry, you usually assume some initial pinout, and modify the pinout if needed (based on how you want the PCB layout to flow, and if you can make the PAL/CPLD/FPGA internal circuity fit given the PCB layout based pinout.

In one extreme, the PCB layout is already done, and you have to constraing the logic device's pinout based on that in your coding. In the other extreme, you code up the device, and give the pinout to the PCB layout person. More generally, you iterate once or twice to optimize the logic device's internal signal routing and to optimize the PCB's layout.