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Homework Help: Quick Question: what is the voltage at this point?

  1. Aug 27, 2010 #1
    1. The problem statement, all variables and given/known data

    [PLAIN]http://img801.imageshack.us/img801/755/bolt.png [Broken]

    3. The attempt at a solution

    Since I have 2 V sources, I think I should use the superposition theorem, that is short +Vdd, get V, short the other , get V, and sum the obtained V's. However, how can I short the sources if I only have a branch? What happens to the end of the branch ?? :confused:

    Thanks in advance!
    Last edited by a moderator: May 4, 2017
  2. jcsd
  3. Aug 27, 2010 #2
    Do you really have two sources?

    Are you able to determine if the diode is forward biased or reverse biased?
  4. Aug 27, 2010 #3
    According to the solution, it is forward biased...
  5. Aug 27, 2010 #4
    Have you studied Kirchoff's current law yet?
  6. Aug 27, 2010 #5
    If it is forward biased, that means the potential you are looking for is negative. But, you will need the characteristics of the diode.
  7. Aug 27, 2010 #6
    Sure. I don't know if I am applying it well or not, anyway KCL:

    IR4 = IR3

    V = VDD (R3-R4)/(R3+R4) which will be negative in order to have the diode on.

    Can it be ok?

    I only know the diode forward voltage, Vd. And, VDD >> VD.

    From there, if 0 - V >= VD (in order to have the diode on),

    and substituting the equations, I finally got the conclusion that R4 >= R3 for the diode to be on...
  8. Aug 27, 2010 #7
    Is there anything in the statement of the problem that indicates the chassis ground is connected to the voltage source? If not, now can you solve the problem?
  9. Aug 28, 2010 #8
    The original circuit of the was the one below. I had to find the states of the 2 diodes when Vout goes from -Vdd to + Vdd.


    So I wanted to know what is the voltage between R4 and R3, to check the state of the diode DA ( such V must be negative since Diode is connected to the virtual ground of the op-amp). According to my solution:

    From KCL at the node between R4 and R3 we get: V = Vdd (R4-R3)/(R4+R3)

    Since a condition for Diode 1 to be on is that its voltage must be greater than Forward voltage ( 0 - V > Vd , and since we know from the problem that Vdd >>> Vd, I reach the following inequation: R3 > R4, which I guess may be a condition for DA to be on.

    What do you think?
  10. Aug 28, 2010 #9
    Your new diagram is quite different from the previous one. Conserningh the latter we can write the following:

    Suppose that DA is inversely biased. Then, from the KCL for the node between R3 and R4, we ought to get:

    \frac{V_{\mathrm{DD}} - V}{R_{4}} + \frac{V_{\mathrm{out}} - V}{R_{3}} = 0

    where V is the potential of that node. Solving for it, one gets:

    V = \frac{R_{3} \, V_{\mathrm{DD}} + R_{4} \, V_{\mathrm{out}}}{R_{3} + R_{4}}

    A similar assumption for DB being inversely polarized leads to the following KCL equation for the node between R5 and R6:

    \frac{V_{\mathrm{out}} - V'}{R_{5}} + \frac{-V_{\mathrm{DD}} - V'}{R_{6}} = 0

    Solve this for for V'!

    In this way, you have the potentials on which the n-terminal of DA and the p-terminal of DB are. You need to find the potential on which the p-terminal of DA and the n-terminal of DB are. From the circuit, you see that both of these terminals are connected at the same node as the "-" input terminal of the OP-AMP (as well as R1 and R2).

    What properties of the OP-AMP is important in deducing the potential of this point?

    After you had found it, what conditions must be met in order that the assumptions made in the beginning that both diodes are inversely polarized are both correct?
  11. Aug 28, 2010 #10
    Thanks for your reply.
    Hmm... I don't think so, since the problem asks you for the states of the diodes when Vout is changed from -Vdd to +Vdd... (In the first diagram I wrote the case of Vout=-Vdd)

    V = \frac{R_{6} \, V_{\mathrm{out}} - R_{5} \, V_{\mathrm{dd}}}{R_{5} + R_{6}}

    By the way, could you please explain me how did you get the KCL? Why are the two currents entering at the node?


    I guess that both diode terminals are connected to a virtual ground, hence 0V.

    V > 0 and V' < 0 ?
  12. Aug 28, 2010 #11
    My two currents are entering the node, so that their sum must be zero.
  13. Aug 28, 2010 #12
    I change my question, Why when the diode is in reversely biased, the 2 currents are entering to the node ?
  14. Aug 28, 2010 #13
    Because there is no current flowing through the diode when it is inversely polarized.
  15. Aug 28, 2010 #14
    Thanks. I understood that since it is reversely biased, the current entering through the diode should be 0. My question is about the direction of the other 2 currents. Why are both of them entering the node ? I thought one was entering, and one was leaving....
  16. Aug 28, 2010 #15
    You can always assume a direction of the current and if you get a negative result it means it flows oppositely of what you assumed.
  17. Aug 28, 2010 #16
    I haven't read this entire thread in detail because it looks like you are getting good help here. However, I feel the need to bring up one point or caution for the future, and a quick scan revealed that maybe no one else has mentioned this yet.

    Someone already pointed out that superposition in this example must first establish if there are two (or more) sources here, which is an appropriate question. However, aside from that issue, you must always keep in mind that superposition only applies to linear systems. Any circuit with a diode is strictly a nonlinear circuit for which superposition does not hold. There are times when you can do a linearization and still salvage the superposition principle, but this must be done with caution.

    Anyway, you may already know this and maybe some comments here hint at this, but I just want to make sure you know and make sure the point is clear.
    Last edited: Aug 28, 2010
  18. Aug 28, 2010 #17
    Ok! Thanks!

    I didn't know about that! Thanks!
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