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Recognizing XOR gates in K-maps

  1. Feb 11, 2013 #1
    Most Karnaugh maps care only about either SoP representations or PoS representations. I have to implement a circuit which minimizes the number of gates and I noticed that certain circuits can be minimized by using XOR gates, although the K-map/Quine-McCluskey technique do not really seem to take the XOR gate into account.

    Why is this? Does anyone know how to read XOR gates off of a K-map, i.e. prime implicants which can be simplified via an XOR gate? I would imagine it has something to do with the "checkerboard" arrangement of the 0s and 1s on the K-map but that is only a tentative guess. I need an expert's opinion.

    Thanks in advance! Really appreciate it.

  2. jcsd
  3. May 20, 2017 #2
    OK, I know this question was posted four years ago, but just to cut down on the overall unanswered question count, here we go...

    I noticed the same thing (many) years ago when I was in my hardware designs course at college. My prof explained that in RTL/TTL circuitry, XOR was essentially three gates' worth of transistors: it boiled down to (A||B)&&!(A&&B)) Additionally, in many cases there were equivalent circuits using JUST and/or operations, so not much effort was put into translating exclusive or ops into hardware. Nowadays, in CMOS, A-and-not-B-OR-B-and-not-A (another way to see XOR) is not vastly more expensive (area wise) than the other(AND/OR) gates.

    IANA silicon slinger
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