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Simple NAND flip flop question

  1. May 11, 2007 #1
    something has always bothered me about nand flip flops and their use in memory so I thought I would ask this here and get it cleared up.

    In a basic nand flip flop like the one found here:
    http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/nandlatch.html#c1
    I understand that there is a stable state Q=1 and Q' = 0, but what I don't get is how this helps in flash memory.

    Once I say pull a usb flash drive out of the computer, it has no more electricity so how can S or R remain 1? In my mind I see the lack of electricity as being a 0 S input and a 0 R input that would put the latch into its invalid state.

    What is the tiny key thing that I am missing to make sense of this?? This has been bugging me all day

    Big thanks in advance,
    lampshade
     
  2. jcsd
  3. May 11, 2007 #2

    berkeman

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    Staff: Mentor

    A simple flip flop (as is used in RAM cells, etc.) is volatile -- the contents are lost when power is cycled.

    Non-volatile memory like flash and EEPROM has other mechanisms for storing charge that stays stored even when the power is turned off. One technique is a "floating gate" technique, where charge is tunneled into a floating, isolated gate, where it stays for many years without leaking out. The presence or absence of the charge on the floating gate affects the transistor characteristics of the associated cell, and can be read out (without affecting the stored charge) in order to tell whether that cell contains a logic 1 or 0.

    http://en.wikipedia.org/wiki/Flash_memory
     
  4. May 11, 2007 #3
    Thanks a ton for the clarification. I had actually already read the wiki page in the process but I was still a little confused.

    Thanks again!
     
  5. May 13, 2007 #4

    cepheid

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    Gold Member

    I've always wondered this too. Thanks for the info. I wonder how the inventer dreamed that up. The floating gate FET idea seems quite ingenious.
     
  6. May 14, 2007 #5

    berkeman

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    Yeah, I agree -- a great invention. And another extension on that, are the zero-mask-adder non-volatile transistor configurations that are getting qualified for viable IP at different geometries right now. That means that various aggressive startup companies are doing their best to prove that they can supply (for a reasonable fee) IP (intellectual property licenses) that enable us chip companies to make chips with non-volatile memory arrays that do not require the extra IC fab layers (and associated cost). Great stuff on the cusp of technology in the Valley (and elsewhere obviously)!
     
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