# Homework Help: Simulating a NAND/AND gate in Emitter Coupled Logic?

1. Mar 9, 2013

### jean28

1. The problem statement, all variables and given/known data
I need to simulate a AND/NAND gate with Emitter Coupled Logic. As i'm sure that most of you know, ECL is mostly used to make OR/NOR gates, so finding out how to make a NAND/AND gate is not as easy as it sounds.

2. Relevant equations

3. The attempt at a solution

I attached an image of a possible model that I found online. However, how do I know which values I should put in order to make the circuit work? How do I know which voltages should be in VBB1, VBB2, etc?

Thanks

#### Attached Files:

• ###### NANDAND.jpg
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2. Mar 10, 2013

### rcgldr

I did a web search and VBB is the bias voltage use to determine if an input is "true" or "false", but I couldn't find the specific voltages.

Last edited: Mar 10, 2013
3. Mar 10, 2013

### CWatters

4. Mar 10, 2013

### jean28

5. Mar 10, 2013

### rcgldr

True, but it does show that VBB for Q3 is -1.29V, while VCC is -5.2V, the same as your AND / NAND circuit. In general, VBB is set to the middle of the .8 voltage difference beween a logic "0" and a logic "1". I found an ECL document that specifies the voltage range for VBB as well as the other voltage ranges:

https://smartech.gatech.edu/jspui/bitstream/1853/32110/1/PG_TR_050518_RJP.pdf [Broken]

Last edited by a moderator: May 6, 2017
6. Mar 11, 2013

### CWatters

I think it will be slightly different for the NAND because if you follow the path from INB to VBB2 there is an aditional Vbe compared to a NOR. It goes...

INA - Vbe -Vbe +Vbe = VBB2

So set INA to mid way between logic 1 and 0 and you can calculate VBB2.

For INB it's..

INB - Vbe + Vbe = VBB1

Basically the principle is that of a differential amp/long tailed pair configured as a comparator (eg one input fixed voltage).

http://en.wikipedia.org/wiki/Differential_amplifier