Engineering Simulating this cascoded NMOS logic circuit

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The discussion revolves around simulating a cascoded NMOS logic circuit to achieve a 100 ps delay while driving a 100 fF load using 0.25 μm devices. Participants emphasize the need for the original poster to demonstrate their approach before receiving detailed assistance. Clarification is sought regarding a specific symbol in the circuit, identified as a "keeper" circuit that prevents floating inputs. The original poster expresses a desire to manually size the NMOS transistors rather than using a simulator, focusing on calculating current for the load capacitor. The conversation highlights the importance of understanding the relationship between aspect ratios and circuit performance in achieving the desired delay.
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Homework Statement
Size and simulate the circuit (IMAGE BELOW) so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs. (VDD = 2.5V) Assume A, B and their complements are available as inputs.
Relevant Equations
vailable common data for nmos are following Vt=0.43(V),Vdsat=0.63(V),k'=115x10^-6 (A/V^2),lambda=0.06(v^-1)
I need help for following exercise from Rabaey - Digital Integrated Circuits: A Design Perspective

Size and simulate the circuit (IMAGE BELOW) so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs. (VDD = 2.5V) Assume A, B and their complements are available as inputs.
Available common data for nmos are following Vt=0.43(V),Vdsat=0.63(V),k'=115x10^-6 (A/V^2),lambda=0.06(v^-1)
Please help me.
2022-02-04_100733.png
 
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Welcome to PF.
Have you yet identified the two input logic function with a complementary output ?
How will you simulate the gate and delay ?
 
Welcome to PF. :smile:

You need to show some effort before we can provide tutorial help. Please show us how you will approach this question.

Also, I'm a little confused by this symbol in the middle of your NMOS logic circuit -- what is it meant to represent? Is it some IP that is defined elsewhere in the problem statement?

1644244984698.png
 
berkeman said:
Also, I'm a little confused by this symbol in the middle of your NMOS logic circuit
It is a memory element made from two soft output inverters.
It retains the last valid state of the gate, so prevents floating inputs consuming current.
 
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Ah, it's a "keeper" circuit. Got it, thanks @Baluncore :smile:
 
Baluncore said:
Welcome to PF.
Have you yet identified the two input logic function with a complementary output ?
How will you simulate the gate and delay ?
I think it's a XOR port for Y and XNOR for Y negate.I don't want to simulate the circuit by a simulator but I want to size (by hand) W/L for NMOS transistors to get a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs.
 
elektro2021 said:
I don't want to simulate the circuit by a simulator but I want to size (by hand) W/L for NMOS transistors to get a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs.
Okay, can you show us how you are going to approach that?
 
elektro2021 said:
I want to size (by hand)
Have you attempted to do that yet?
 
I think that I need to compute current charge/discharge for 100 fF capacitor...what do you think?
 
  • #10
Any help?
 
  • #11
elektro2021 said:
Any help?
You go first... :wink:
 
  • #12
I think that Ic=C*(dv/dt) con C=100 fF and dv/dt= (VDD/2)/T con T=100ps and VDD=2.5V...what do you think?
 
  • #13
So after you determine the voltages and currents involved, how will you choose the aspect ratio for your geometry?

elektro2021 said:
I want to size (by hand) W/L for NMOS transistors to get a 100 ps delay (50-50) using 0.25 μm devices
 
  • #14
I don't know...I think that NMOS current depends by W/L...please help me
 
  • #15
We *are* trying to help. What do your class notes say about aspect ratio effects on voltages and currents?
 

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