EST Find Current IDs for NMOS-PMOS Circuit

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  • Thread starter brad sue
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In summary, the speaker is seeking assistance with a problem that the teacher hinted may appear on an exam. They have simulated the circuit using Pspice and have found values for IDS and Vout. They are struggling to find the values using the saturation formula and have had trouble graphing the load line for one of the transistors. They are looking for help in solving the problem and have been advised to make equations for each MOSFET.
  • #1
brad sue
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HI,
The teacher gave us an hint about a problem that might appear on an exam.
I was not able to solve it and I need some assistance pleas.
Find the current ids for the following circuit:
see attachment.

I have simulated the circuit with Pspice and I get the following values ids= 2.75[mA]
and Vout=4.32[V]

the paramter for the transistors were:
NMOS Kp=500 [uA/V^2]and Vto=1[V]

PMOS Kp=500 [uA/V^2] Vto=-1[V]

I tried the saturation formula but I did not find the values.

I also tried to use the load lines for the transistors but I had trouble graphing the load line for the NMOS (bottom transistor).
Please can someone help me please?
Thank you
B
 

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  • #2
You have two unknown variables in this problem IDS and VO. You can also make two equations, one for each MOSFET. Like IDS = KP⋅(VGS - VTO). Find VGS in terms of the circuit voltages. Of course IDS will be the same for both transistors since there's no load.

You can start with the assumption that both devices are operating in their linear region, but then verify that is true after you get a solution.
 

Related to EST Find Current IDs for NMOS-PMOS Circuit

1. What is EST in regards to NMOS-PMOS circuit?

EST stands for equivalent series resistance, which is the sum of all the resistances within a circuit. In an NMOS-PMOS circuit, it is important to calculate the EST in order to properly analyze and design the circuit.

2. How do I find the current IDs for an NMOS-PMOS circuit?

To find the current IDs for an NMOS-PMOS circuit, you will need to use the equation Ids = (k/2)*(Vgs-Vth)^2, where k is the transconductance parameter and Vth is the threshold voltage. You will also need to consider the EST in your calculations.

3. Why is it important to calculate the EST for an NMOS-PMOS circuit?

The EST is an important factor to consider in an NMOS-PMOS circuit because it affects the overall performance and efficiency of the circuit. If the EST is too high, it can lead to decreased current and voltage levels, resulting in a less efficient circuit.

4. What factors affect the EST in an NMOS-PMOS circuit?

The EST in an NMOS-PMOS circuit can be affected by factors such as the size and geometry of the transistors, the material used for the transistors, and the layout of the circuit. It is important to consider these factors when designing the circuit to achieve optimal EST.

5. Are there any methods for reducing EST in an NMOS-PMOS circuit?

Yes, there are several methods for reducing EST in an NMOS-PMOS circuit. Some of these methods include using smaller transistors, optimizing the layout of the circuit, and using materials with lower resistivity. It is important to carefully consider these methods in order to achieve the desired EST for the circuit.

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