Square wave, sampling and verilog clocks

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Homework Statement



lab1questions.png


Homework Equations



My question too :)

The Attempt at a Solution



20121203_001023.jpg


Can anybody confirm whether I solved the problem right or wrong? As for the next question about verilog and many clocks I am unable to find a source with that information. Thanks a lot for any help.
 

Answers and Replies

  • #2
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After reading the question about the square wave again, I wonder if a better answer would be as follows:

100/20 = 5. Because the duty cycle is at least 20%.

Then we find 5% of 20% which is 0.05*20=1%. Because the sampling signal must cover 95% of the H value of the square wave. This means that the signal frequency must be 1% of the sampling frequency.

So 10 kHz*100=1000 kHz...

Anyone know if I got it right this time?
 
  • #3
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I don't quite follow what you were doing but I come up with 1MHz as well by a different way:

Th is smaller than Tl so a max 5% error will be more restricting on the Th parameter.

The error in measured Th is Ts/Th, sample period = Ts, because Ts is the maximum time that can go by between the actual signal changing and the sampler detecting that change.

So:

Ts/Th < 0.05

Th = D*T (duty cycle times period) and is smallest at 20% duty cycle and 10kHz period

Ts < 0.05*Th = 0.05*0.2/10kHz
Fs = 1/Ts > 1 MHz

If you had more than one period to look at this signal, the sample rate could probably go lower.



As for your verilog question, matters do complicate when signals are communicated across clock domains. This is because there is no synchronization between two separately generated clocks. You don't know how much they are displaced in phase and that phase will drift too. So when one signal from clock domain C1 is communicated to clock domain C2, the arriving signal will be valid at a poorly controlled point in C2's period. If the arriving signal is changing as a flip flop in C2's domain samples on its rising C2 edge, metastability will occur. Metastability occurs when a signal is sampled close to the 50% level (half way between a 0 and 1). The closer the signal is to the 50% level, the longer it takes the output of the sampling flip flop to settle to a value. The time is in fact exponential so an input signal very close to 50% may cause the output of this sampling flip flop to be close to 50% on the next sampling in the C2 domain, causing an uncertain signal to propagate into the second domain. Garbage in, garbage out.

The usual recourse is to have signals crossing clock domains to pass through two or three flip flops that only sample the incoming signal on the C2 clock before passing it into the C2 domain. This reduces the chances of propagating a metastable signal at the expense of introducing several periods in delay.

Long story short, operate with a single clock whenever possible to avoid this problem. Perhaps metastability was mentioned in your course.
 

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