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frankfjf

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## Homework Statement

I've already figured out the code for part 1 of the assignment. I'm stuck on part 2. Specifically, I'm not sure how one would obtain the values for the multiplier and multiplicand from R6, as the notes from the professor in the code claim, nor how to format the result in doubleword ACC:MPR.

Specifically, I'm unclear on how the whole argument list being passed to UNSMUL in R6 part works. Am I missing some code? When I step through it using the LC3 Simulator, I get nothing being passed to the registers in UNSMUL with regards to obtaining the multiplier and the multiplicand. I have the feeling I need to do something with the subroutine call, but I'm not sure what.

Problem Statement

Implement and test

1) Subroutine SHIFTR to perform a logical right shift on R0

2) Subroutine UNSMUL to multiply a pair of unsigned words and return the double-word product.

## Homework Equations

The professor gives the following details/notes for the mentioned part of the assignment:

Extended Unsigned Multiplication

1. Apply the algorithm described in Note 17 on the class page.

2. Modify the implementation to take into account a carry produced at the addition step of the algorithm. If there is a carry, set the high-bit of the shifted ACC.

Under Specific Instructions for the Extended Unsigned Multiplication part, he writes:

• The UNSMUL subroutine has 3 parameters 1) the multiplier, 2) the multiplicand, and 3) the address for the double-word product. These must be prepared by the caller in an argument-list in memory. The address of the argument-list is passed to UNSMUL in R6.

• A start-up source file is provided. You will need the OR, XOR and OFLO subroutines from the previous assignment.Note 17:

General Multiplication Algorithm

================================

Obtains the double-length product of a pair of N-bit unsigned integers.

MPR : Multiplier MND : Multiplicand ACC : Accumulator

The algorithm treats ACC as a high-end extension of MPR

1: MPR := multiplier //Initialize

MND := multiplicand

ACC := 0

2: LOOP N times //Iterate

2.1: IF (low-bit of MPR = 1) //Test

2.1.1: ACC := ACC + MND //Add

2.2: SHIFT (ACC:MPR) right once //Shift

ENDLOOP

3: Product is available in ACC:MPR

## The Attempt at a Solution

Here is my code thus far, including the professor's comments and my own on how it should work. As I said before, my problem seems to be figuring out how to get the multiplier and multiplicand values out of memory so I can work with them, and then generating the product in the specified format and putting it where it needs to go.

Code:

```
.ORIG x3000
LD R4, PRINT
LD R5, PRNTLN
;Testing the SHIFTR subroutine
LD R0, X
JSRR R5 ;Println(X)
JSR SHIFTR
JSRR R5 ;Println(ShiftR(X))
;Testing the UNSMUL subroutine
LEA R6, ARGS
;
;Prepare the argument list for a call to UNSMUL
;
JSR UNSMUL ;A x B
LD R0, A
JSRR R5 ;Println(A)
LD R0, B
JSRR R5 ;Println(B)
LD R0, ABHI
JSRR R4 ;Print(HighWord A x B)
LD R0, ABLO
JSRR R5 ;Println(LowWord A x B)
TRAP x25
ARGS .BLKW 3 ;Argument-list for UNSMUL
X .FILL xABCD
A .FILL 20
B .FILL 10
ABLO .BLKW 1 ;Low-word of A x B
ABHI .BLKW 1 ;High-word of A x B
PRINT .FILL x5000
PRNTLN .FILL x5005
SHIFTR ;Perform a Shift-Right on R0
ST R1, SHIFTR1
ST R2, SHIFTR2
ST R3, SHIFTR3
ST R4, SHIFTR4
ST R7, SHIFTR7
AND R1, R1, #0 ;Clearing R1 for the shifted result.
ADD R1, R0, R1 ;Placing contents of R0 into R1.
AND R0, R0, #0 ;Clearing R0 for containing shifted result later.
LD R2, STMASK ;Setting Test Mask (STMASK) and Set Mask (SSMASK), respectively.
LD R3, SSMASK
SHIFT1
AND R4, R1, R2
BRZ SHIFT2
ADD R0, R0, R3
SHIFT2
ADD R2, R2, R2
ADD R3, R3, R3
BRNP SHIFT1
LD R1, SHIFTR1
LD R2, SHIFTR2
LD R3, SHIFTR3
LD R4, SHIFTR4
LD R7, SHIFTR7
RET
SHIFTR1 .BLKW 1 ;Register save area
SHIFTR2 .BLKW 1
SHIFTR3 .BLKW 1
SHIFTR4 .BLKW 1
SHIFTR7 .BLKW 1
STMASK .FILL x02
SSMASK .FILL x01UNSMUL ;Unsigned Multiplication
;Argument-list in memory located by R6
; R6[0] multiplier value
; R6[1] multiplicand value
; R6[2] product address
ST R1, UMUL1
ST R2, UMUL2
ST R3, UMUL3
ST R4, UMUL4
ST R5, UMUL5
ST R6, UMUL6
ST R7, UMUL7
LDR R1, R6, #0 ;R1 = MPR
ADD R6, R6, #1
LDR R2, R6, #0 ;R2 = MND
AND R3, R3, #0 ;R3 = ACC
LD R4, UTMASK
LD R6, UCOUNTUMLOOP
AND R5, R1, R4
BRZ UMST1
ADD R3, R3, R2
UMST1
ADD R0, R3, #0
JSR SHIFTR
ADD R3, R0, #0
ADD R0, R1, #0
JSR SHIFTR
ADD R1, R0, #0
ADD R6, R6, #-1
BRNP UMLOOP
LD R1, UMUL1
LD R2, UMUL2
LD R3, UMUL3
LD R4, UMUL4
LD R5, UMUL5
LD R6, UMUL6
LD R7, UMUL7
RET
UMUL1 .BLKW 1 ;Register save area
UMUL2 .BLKW 1
UMUL3 .BLKW 1
UMUL4 .BLKW 1
UMUL5 .BLKW 1
UMUL6 .BLKW 1
UMUL7 .BLKW 1
UHOLD .BLKW 1
UTMASK .FILL x0001
UCOUNT .FILL x0008OR ;R0 = R1 or R2
ST R7, OR7
ST R4, OR4
ST R3, OR3
NOT R3, R1
NOT R4, R2
AND R0, R3, R4
NOT R0, R0
LD R3, OR3
LD R4, OR4
LD R7, OR7
RET
OR3 .BLKW 1
OR4 .BLKW 1
OR7 .BLKW 1
XOR ;R0 = R1 xor R2
ST R7, XOR7
ST R4, XOR4
ST R3, XOR3
ST R2, XOR2
ST R1, XOR1
NOT R3, R1
NOT R4, R2
AND R1, R1, R4
AND R2, R2, R3
JSR OR
LD R1, XOR1
LD R2, XOR2
LD R3, XOR3
LD R4, XOR4
LD R7, XOR7
RET
XOR1 .BLKW 1
XOR2 .BLKW 1
XOR3 .BLKW 1
XOR4 .BLKW 1
XOR7 .BLKW 1
OFLO ;R0 = 0000 0000 0000 00vc
; c = Carry(R1 + R2)
; v = Overflow(R1 + R2)
ST R7, OFL7
ST R6, OFL6
ST R5, OFL5
ST R4, OFL4
ST R3, OFL3
ST R2, OFL2
ST R1, OFL1
ADD R3, R1, R2 ; R3 = a + b
AND R4, R1, R2 ; R4 = a and b
JSR XOR
ADD R5, R0, #0 ; R5 = a xor b
ADD R2, R3, #0
JSR XOR
NOT R2, R5
AND R6, R2, R0; ; R6 = overflow
NOT R3, R3
AND R2, R3, R5
ADD R1, R4, #0
JSR OR
ADD R5, R0, #0 ; R5 = carry
AND R0, R0, #0
ADD R5, R5, #0
BRZP L1
ADD R0, R0, #1
L1
ADD R6, R6, #0
BRZP L2
ADD R0, R0, b10
L2
LD R1, OFL1
LD R2, OFL2
LD R3, OFL3
LD R4, OFL4
LD R5, OFL5
LD R6, OFL6
LD R7, OFL7
RET
OFL1 .BLKW 1
OFL2 .BLKW 1
OFL3 .BLKW 1
OFL4 .BLKW 1
OFL5 .BLKW 1
OFL6 .BLKW 1
OFL7 .BLKW 1 .END
```

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