Successive Approximation ADC: What Sets It Apart?

[Femme_physics]

Wiki says:

A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion.

Isn't this exactly what every A/D converter does?

For a graph of Vin to digital output it basically approximates the nearest digital value to the continuous signal ->

So I don't see the difference between them.

 

[I like Serena]

Yes, that is what every A/D converter does.

The difference is in how the A/D converter works internally, which has an implication on the performance it can give.

A successive approximation ADC uses 1 comparator and counts towards the signal.
This means a long conversion time.
And it won't be able to follow a signal that makes "jumps" correctly.

A direct-conversion ADC uses a bank of comparators to instantaneously convert the signal.
This implies a short conversion time, and it can follow jumps.
But it will be more expensive.

 

[256bits]

There is no such thing as a 'regular' ADC.
Each has its pros and cons depending on if you want speed of conversion, cost or resolution, etc.

If you look at this site on DAC and ADC it describes the many types.
http://www.faqs.org/docs/electric/Digital/DIGI_13.html

 

[yungman]

There is no such thing as a 'regular' ADC.
Each has its pros and cons depending on if you want speed of conversion, cost or resolution, etc.

If you look at this site on DAC and ADC it describes the many types.
http://www.faqs.org/docs/electric/Digital/DIGI_13.html

Yes, there are different type of ADC, bottom line is speed vs simplicity.

 

[Femme_physics]

A successive approximation ADC uses 1 comparator and counts towards the signal.
This means a long conversion time.
And it won't be able to follow a signal that makes "jumps" correctly.

A direct-conversion ADC uses a bank of comparators to instantaneously convert the signal.
This implies a short conversion time, and it can follow jumps.
But it will be more expensive.

So a successive approximation is basically less accurate than direct-conversion ADC?

Is it essentially the cheaper junk of the ACD market since it uses more cheap and archaic methods?

 

[I like Serena]

So a successive approximation is basically less accurate than direct-conversion ADC?

Is it essentially the cheaper junk of the ACD market since it uses more cheap and archaic methods?

Yep. :)

 

[jim hardy]

in real world environment a dual slope integrator with integration period of one power line cycle offers some benefits wrt line frequency noise rejection. But it's painfully slow.

 

[Femme_physics]

Well, I am supposed to explain the principle of how successive approximation works. And I need to demonstrate this explanation. I'm sorry it appears like a HW is intruding, but that's what sparked it all.

I am tempted to just quote ILS. Problem is, even if I do, I need to demonstrate this successive approximation explanation based on the following A/D converter

http://img715.imageshack.us/img715/8844/dact.jpg

There are no comparators and no counters that I can see...

 

[jim hardy]

Bassalisk had very similar thread a few weeks ago.
https://www.physicsforums.com/showthread.php?t=566035&highlight=adc+bassalisk
It had some good links.

See if this one is any help. Seems to have the right title.
http://www.allaboutcircuits.com/vol_4/chpt_13/6.html
Read 'Previous Page" in that link because it builds on an idea presented there.

That looks more like a DAC in your post. They wrap a loop around it to make it do ADC, as the link shows.

 

[Femme_physics]

Thanks :)

Yep. :)

According to the link "jim hardy" provided:

One method of addressing the digital ramp ADC's shortcomings is the so-called successive-approximation ADC. The only change in this design is a very special counter circuit known as a successive-approximation register. Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the most-significant bit and finishing at the least-significant bit. Throughout the count process, the register monitors the comparator's output to see if the binary count is less than or greater than the analog signal input, adjusting the bit values accordingly. The way the register counts is identical to the "trial-and-fit" method of decimal-to-binary conversion, whereby different values of bits are tried from MSB to LSB to get a binary number that equals the original decimal number. The advantage to this counting strategy is much faster results: the DAC output converges on the analog signal input in much larger steps than with the 0-to-full count sequence of a regular counter.

Why would they compliment this successive approximation method if it sucks so much?

 

[jim hardy]

Ahhh those sneaky fellows . The key word is in your post #1, "" via a binary search ""
In "Previous Page" at that link they describe an ADC that uses a free running counter which starts at 0 and increments one LSB at a time until it reaches the value of input. For 8 bits it would take 256 counts to digitize a full scale analog input. 128 for a half scale input.
The cycle stops after however many tries it took , max being 2^(number of bits).

The successive approximation starts instead with MSB and words sort of fail me here. So let me do an example.
Assume the analog input is full scale , 256 for our 8 bit example.

Set MSB only, that's halfscale and comparator recognizes that's not a big enough number.
So set next MSB, still not big enough
Set next MSB, still not big enough
and so on
until you set LSB and comparator recognizes that as the proper result., all bits set .
So you arrived at answer with eight tries instead of 256.

That's a binary search - where you eliminate half your choices with each test.
Had the number been too large at any point you'd just not set that bit and go on until all eight bits were tested.So the successive approximation is usually faster than simple up-counter and perhaps a kind word for it is not out of order.
Certainly it's more predictable. It'll always take 8 trial cycles whereas the simple up-counter takes however many cycles are required to reach input - not many for small numbers but lots for large ones.

Recognizing that 8 bits is not a lot of resolution and even 256 tries wouldn't be outlandish. But what about those eighteen bit ADC's ?

did i get it across? Sorry for my ineloquence. I was "Born to Plod."

old jim

 

[I like Serena]

According to the link "jim hardy" provided:

Why would they compliment this successive approximation method if it sucks so much?

Because it improves on the 0-to-full count method (which you have in your other thread) beautifully and it's a gem in engineering design. ;)

Of course in electronic equipment where it counts (like audio), you'll only see direct-conversion A/D's.

 

[Femme_physics]

In other words, there are many much more plenty fancy stuff, huh? :)