Switching window in comparators

Staff Emeritus
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I'm looking for a complete definition of the switching window in the context of comparators.

In particular, I want to make sure I'm not misunderstanding how hysteresis is implemented in the AD630 (Analog Devices) chip.

See page 2, in the spec table for the comparator, where the switching window is specced. Also see page 6, under 'Circuit Description', where it says:

This structure is designed so that a differential input voltage greater than 1.5 mV in magnitude
applied to the comparator inputs will completely select one of the switching cells. The sign of this input voltage determines which of the two switching cells is selected.
Does this mean that no switching will occur until the 1.5 mV differential signal is exceeded? In other words, if one input is grounded, and the other input has a stable sine wave, then switching will occur exactly at 1.5 mV above (below) the zero crossing during the increasing (decreasing) half-cycle? Also, this should introduce a phase shift of roughly 10-3 in the output for say, a 1V input signal. Is that right?

And finally, what is the point of this? The only sense I can make out of it is that it avoids instability around the zero-crossings due to noise in the input signal. But this is already taken care of by the recommended hysteresis circuit in (figure 7) page 8. If I understand that part correctly, it makes the output switch at a differential signal of 0.5 mV (above and below zero). Why would they recommend a 0.5 mV hysteresis circuit, when the chip has a built in 1.5 mV "safety window."

I think my understanding of the term 'switching window' is flawed. Does it in fact mean that switching could happen anywhere within the 1.5 mV window beyond zero, with an essentially 100% probability of switching beyond the window, and some non-zero (maybe sigmoidal) probability distribution within it? What other mistakes am I making in my reasoning?

Please be gentle with me - I'm not traditionally trained in electronics.

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dlgoff
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It looks like the switching window is the range of voltages that can be applied to the inputs based on the supply voltages ( -Vs to +Vs) with a ±1.5mV variation from chip to chip.

"And finally, what is the point of this? The only sense I can make out of it is that it avoids instability around the zero-crossings due to noise in the input signal. But this is already taken care of by the recommended hysteresis circuit in (figure 7) page 8."

As shown it looks like you are correct in it being about 0.5mV but you might want to use the circuit to get a larger hysteresis by changing the resistors. It's just an example.

Regards

Staff Emeritus
Gold Member
It looks like the switching window is the range of voltages that can be applied to the inputs based on the supply voltages ( -Vs to +Vs) with a ±1.5mV variation from chip to chip.
I don't think I'm following you here. This doesn't seem consistent with the bit I quoted from page 6 or with the line in the spec table that says the window itself is ±1.5mV. Or maybe, I've misunderstood what you're saying.

As shown it looks like you are correct in it being about 0.5mV but you might want to use the circuit to get a larger hysteresis by changing the resistors. It's just an example.
Yes, though in my case, I don't think I will need any more than that - my signal is very clean with noise < 10ppm. But this raises a related question. If I had say, 10 muV (pk-to-pk) noise on my input, then that's a maximum time interval between noise spikes of dT = V(noise)/(slope at V=0) = 10 muV/ (2Vo*pi*f) which is only about 200 ns even at low frequencies (~20Hz). Do comparators even switch that fast? Figure TPC 8 (bottom of page 5) doesn't seem to give me a conclusive answer. I recall that gate charging time in a typical FET is of order 100 ns. So the question is this: Do I even need a hysteresis adjustment if my noise is this low?

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berkeman
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