Two types of edge-triggered flip flop?

[stug]

I've lately been going through the Nand2Tetris course since I never had the chance to take anything like it in college, and in its chapter on sequential logic , it treats the D flip-flop as a fundamental component. I found that somewhat unsatisfying, so I went and started reading up on flip-flops and latches, and have found two seemingly analogous ways to make a positive-edge triggered flip-flop, which Wikipedia refers to as "classical" and "master-slave".

I was wondering if there was any reason that one gets used over the other (other than the fact that the "classical" version seems to employ fewer gates). Any insight would be appreciated!

 

[meBigGuy]

In CMOS, master slave is most common but implemented using inverters and transmission gates (for area and performance).
http://www.play-hookey.com/digital/alt_flip_flops/cmos_d_flip-flop.html

I've never gone through and traced the timing paths for the 2 gate level approaches to see if minimum clock pulse width, setup, hold, and propagation delay times are any different due to the architecture. You might also consider what it takes to implement a set and reset function.

 

[analogdesign]

The VAST majority of D flip-flops used in industry are Master Slave type, as linked to by meBigGuy. The only time the "classical" approach is used is in special circumstances such as in a comparator or in the sense-amplifier of a memory circuit.

The reason the transmission gate style is used is that it is much easier to verify its clocking relationship, so it is easier for a computer to place and route. The vast majority of digital logic these days is described using a high-level language (VHDL or Verilog) and then a computer program actually designs the circuit for you. That is why the author treats the D Flip-Flop as a fundamental brick. Unless you're pushing the edge of performance, most professional designers treat it the same way.

For highest speed using rail to rail swings, check out True Single Phase Clock-style flip-flops. For the maximum speed in a process, current-mode logic (CML) is used. It's work looking up these because they are interesting, and you're learning for fun, right?