Is it possible to have a positive or negative edged J-K master slave flip flop?

  • Thread starter Thread starter Amith2006
  • Start date Start date
  • Tags Tags
    Flip flop Master
Click For Summary
SUMMARY

Edge-triggered J-K master-slave flip-flops can indeed be configured to operate with either positive or negative edges. In a clocked J-K master-slave flip-flop, the master can be positive edge-triggered while the slave is negative edge-triggered, or vice versa. The output assertion depends on the clock edge: if asserted on the falling edge, it is negative edge-triggered; if on the rising edge, it is positive edge-triggered. The truth table should reflect the appropriate clock edge symbol based on this configuration.

PREREQUISITES
  • Understanding of J-K flip-flop operation
  • Familiarity with edge-triggering concepts in digital electronics
  • Knowledge of timing diagrams and their significance
  • Basic skills in creating and interpreting truth tables
NEXT STEPS
  • Study the design and implementation of J-K flip-flops using timing diagrams
  • Learn about the differences between positive and negative edge-triggered flip-flops
  • Explore the creation of truth tables for various flip-flop configurations
  • Investigate practical applications of J-K flip-flops in digital circuits
USEFUL FOR

Electronics students, digital circuit designers, and engineers interested in mastering flip-flop configurations and their applications in synchronous systems.

Amith2006
Messages
416
Reaction score
2

Homework Statement


Does an edge triggered J-K master slave flip flop exist? In a clocked J-K master slave flip flop, the master may be positive edge triggered and the slave may be negative edge triggered or vice versa. Can this flip flop be called an edge triggered J-K master slave flip flop?If so,is it positive edge triggered or negative edge triggered?Then what about the truth table? In the column of clock in the truth table, should a pulse symbol or positive edge or negative edge be drawn?



Homework Equations





The Attempt at a Solution

 
Physics news on Phys.org
... you forgot section 3.
 
whoa hold on there that's a lot of questions in one.

basically it is possible to have either a positive or negative edged flip flop. The equation for the inputs is derived from the timing diagram. If an output is asserted on the falling edge of the flip flop its negative edge triggered (as it goes from positive to negative) - else its asserted on the rising edge of the clk cycle and its a positive edged triggered flip flop

So how are these questions dealt with ?

Heres an example i posted earlier.
not the best example - its all i could find now - but see how the implementation is done - using a timing diagram:

http://img519.imageshack.us/img519/6614/lect3kw5.jpg
http://img261.imageshack.us/img261/5708/lect31ry3.jpg

so in essence - theoretically a JK flip flop or any flop flop can be edge triggered and its design implementation will thus come from its timing diagram (or take that into account)
 
Last edited by a moderator:

Similar threads

  • · Replies 6 ·
Replies
6
Views
6K
Replies
1
Views
4K
  • · Replies 7 ·
Replies
7
Views
7K
  • · Replies 1 ·
Replies
1
Views
2K
  • · Replies 2 ·
Replies
2
Views
4K
Replies
22
Views
6K
Replies
1
Views
3K
  • · Replies 7 ·
Replies
7
Views
7K
  • · Replies 2 ·
Replies
2
Views
4K
  • · Replies 4 ·
Replies
4
Views
5K