Understanding Clamping Diodes: Voltage Conditions and Operational Behavior

[likephysics]

I am trying to understand when clamping diode (at TTL gate input) works and when it does not.
The voltage is -2v at cathode and 0v at anode. Fwd bias condition, but the diode does not condut, until the current is reduced.
Why so?
Initially I thought it was because of the fast rise/fall times (1ns), but now in simulation as I reduce the current, it starts to clamp.
Ckt diagram attached. Please ignore the component values.
Current is reduced using Resistor R3.
C1 and R4, produce undershoots. Just a high pass filter with 5Vpk-pk square wave input.

 

[dlgoff]

Here's a diode clamp diagram the might help:

Zener diodes can also clamp and limit the voltage:

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/limiter.html"

 

[likephysics]

dlgoff, My question was why does it conduct only when I reduce the current?

 

[dlgoff]

dlgoff, My question was why does it conduct only when I reduce the current?

If you mean reducing the current through the diode in your simulation, you need to understand that a diodes IV curve isn't linear. For silicon diodes, forward biasing conduction begins at about 0.5 volts and when you get to about 0.7 volts and above, the current increase very quickly.

http://hyperphysics.phy-astr.gsu.edu/hbase/solids/diod.html"

For real diodes, if you forward bias at 2 volts, the current is so high the diode will open due to failure.