Understanding Digital Logic Latches: RS, Gated, D Latch Timing Explained

[DiamondV]

Homework Statement

So we've started digital logic in lectures and don't seem to understand some things about it. I've searched online but nobody seems to have explained some things.

RS LATCH

GATED LATCH

D LATCH TIMING

Q1: Does LATCH response(as in truth tables) just mean that nothing will change?i.e its going to remember previous inputs?

Q2: In reference to the last row of inputs in the truth table for an RS Latch and Gated Latch, S and R are both 1 but the Q and Qbar are 0? Why is that? Should they not be remembering the 1 and 1 new inputs?

Q3: In reference to the Gated Latch, is the E(enable) input only to tell the circuit to remember the inputs of S and R? So the only time the circuit will remember what inputs its given is if the Enable Input is 1 aswell? Whats the actual purpose of it?

Q4: I have no idea what these timing diagrams are supposed to tell me? Are they just a visual representation of a truth table? Whats going on?

Homework Equations

The Attempt at a Solution

 

[cpscdave]

Q1: Does LATCH response(as in truth tables) just mean that nothing will change?i.e its going to remember previous inputs?

Ever wonder in a SR latch what the S and the R stand for? Set and Reset. Once I realized that it made a lot more sense!

Q2: In reference to the last row of inputs in the truth table for an RS Latch and Gated Latch, S and R are both 1 but the Q and Qbar are 0? Why is that? Should they not be remembering the 1 and 1 new inputs?

Reset overides Set in this case. The only difference with the gated SR Latch is it has an Enable input as well.

Q3: In reference to the Gated Latch, is the E(enable) input only to tell the circuit to remember the inputs of S and R? So the only time the circuit will remember what inputs its given is if the Enable Input is 1 aswell? Whats the actual purpose of it?

The inputs to the LATCH become S&E and R&E so if E is 0 what are you inputs? S=0 R=0 so you'll get whatever the previous value was :)

Q4: I have no idea what these timing diagrams are supposed to tell me? Are they just a visual representation of a truth table? Whats going on?

A timing diagram shows you how the logic behaves when various inputs are given. From it you can tell things like whether the logic is rising edge or falling edge triggered. As you get into this more it will tell you about delay propogations as well.

 

[DiamondV]

Ever wonder in a SR latch what the S and the R stand for? Set and Reset. Once I realized that it made a lot more sense!
Reset overides Set in this case. The only difference with the gated SR Latch is it has an Enable input as well.
The inputs to the LATCH become S&E and R&E so if E is 0 what are you inputs? S=0 R=0 so you'll get whatever the previous value was :)
A timing diagram shows you how the logic behaves when various inputs are given. From it you can tell things like whether the logic is rising edge or falling edge triggered. As you get into this more it will tell you about delay propogations as well.

Q1: So basically. Reset rests all values back to the defaults?(Q default would be 0 and Qbar would be 1?).

Q2: Following from that default logic above, if reset overides set then why is Qbar now 0?

 

[cpscdave]

Q1) Yup
Q2) It's considered an invalid set of inputs :)

 

[DiamondV]

Q1) Yup
Q2) It's considered an invalid set of inputs :)

Awesomee. thanks so much. this cleared up so many things. :)

 

[cpscdave]

No worries

Check out http://www.cburch.com/logisim/ its a free simulator for digital logic. I found it quite helpful to set up circuits in there and see how they behave. Made it easier for me to wrap my head around things!