# Valid and Invalid interconnections

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1. Aug 13, 2017

### marsupial

1. The problem statement, all variables and given/known data

My question is about the following circuit:
https://ibb.co/hWnb9v

According to the answer, it is an invalid circuit as the voltage drop on the left totals 14V and on the right totals 16V, and they have to be the same between any two terminals. I understand that it has to be so, but it raises many questions for me:

Could you also compare the bottom and top as well, so that would be 30V (8V, 10V, 12V) compared to 10V across the top (6V and 4V), so it would also be invalid from that comparison? And what about just the left side - there you have 6V and 8V next to each other. Is that also similarly invalid?

What about this circuit: https://ibb.co/g7fJNF I know it is valid, but there you have 3 different voltage sources next to each other with a current source, and they are considered as a whole but valid. I just don't fully understand the application of the concept, why in one scenario it is invalid and in another valid.

2. Relevant equations

3. The attempt at a solution
I know the solution as the answer was posted online but I do not understand why it is so in one instance but not another.

2. Aug 13, 2017

### cnh1995

Use the "UPLOAD" button below to post images directly in the thread.

Only the outermost loop containing four voltage sources (8V, 6V, 4V, 12V) makes this circuit invalid.
If the 8V source were 10V instead, the circuit would be valid.

To be valid, a circuit has to satisfy KVL in all the loops and KCL at all the nodes. Check this for both the circuits.

3. Aug 13, 2017

### marsupial

Thank you, that makes so much more sense. I was wondering how to embed images too :-) I had tried in the post but it didn't work.