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Voltage step response of impedance frequency response

  1. Oct 16, 2011 #1
    I am a bit unsure about terminology and method, so I would like to discuss this with anyone who knows anything about this.
    I'm examining the properties of a network of parallel capacitors. I have calculated an impedance versus frequency curve, Z(f), using complex impedance of the capacitors capacitance, inductance and resistance (using octave and the Frequency Domain Target Impedance method (FDTI)). The next property I would like to examine is the step response to a 1 ampere step of this filter(correct term?), with a 0.8 ns 10%-90% rise time. This would give me a voltage as a function of time, v(t). The actual property I want to know is how the system responds (in volts) to a number of digital switches that turns on and together sinks 1 ampere.
    If I understand this correctly, the way to do this is to create a step function,i(t), with the specified properties and make a fourier transform of this, I(f). Next step would be multiplying I(f) and Z(f), to get V(f). By doing an inverse fast fourier transform of this, I would get the step response voltage, v(t).
    Assuming my reasoning is correct, what would be the best i(t) to use? A Heaviside step function seems to be impractical to use on an actual, physical system. If understand this correctly, a gaussian step would be practical and close to the actual physical step?
    Is the method I'm describing correct, and if so, does it have a name so that I can look it up in the litterature? What I'm looking for is a method for actually calculating v(t) mainly using fft and ifft, not doing a mathematical model.
  2. jcsd
  3. Oct 16, 2011 #2
    If you are trying to find the v(t) of a current of 1A switch on at t=0, you don't need Fourier transform. I don't know how detail you want, whether you want to take into consideration of the parasitic of the capacitors, the length of the connecting wire or so. But normally on charging cap, we don't exactly take the wire lengths into consideration. If you really want, you can put in the parasitic of the cap. that would only effect the initial when the current first switch on. After that, it should be just the simple V=IXt.

    At least this is how I look at it. The graph should just have very little ringing at the first few nano seconds and become a linear ramp after that. Cap charged by a constant current of 1A will only produce a linear ramp. the ring at the very beginning is due to the parasitic lead inductance. After the current stabilized, it is just simple current charging a cap!!!
  4. Oct 16, 2011 #3
    Well, I am interested in what happens at the very beginning. I want to compare different capacitor systems, not only looking at frequency impedans response, but also transient noise. I basically want to do what Istvan Novak is doing in this paper: http://www.electrical-integrity.com/Paper_download_files/DC06_TF-MP3_SUN.pdf
  5. Oct 16, 2011 #4
    I did not read the whole article, I read the introduction and go a little deeper. If my assumption is wrong, then ignore me all together. Here is my observation:

    He is talking about how to clean up the power supply. I have been doing EMC design for many years on pcb. He talked about you have to parallel caps of different values usually at about 10:1 or up to like 50:1 value ratio because of the ESR. The larger the cap, the effectiveness goes down with frequency. so you put a smaller value cap to pick up where the larger one left off. Then you put even a smaller value on top etc. In my pcb design for RF circuits, the last on I use is actually a small copper plate right at the power pin of the RFIC to form a parallel plate capacitor with the ground plane underneath. This would be the highest frequency bypass cap.

    I did not get to the last part of the article, but he was talking about power plane and ground plane inside the board. This is the essential part of the EMC design!!! When you design board for RF EMC design, you have to look at any break of the power plane. To every signal, there has to be a return path called image current. In EM, you want to make the current loop area as small as possible. If there is a break, the current will have to find the next closest path and the loop area increase and more radiation. What I do is if I have to put multiple power planes in one layer, I try to put them sandwich between two ground plane and put bypass caps along the edge of the power planes to let the current path continue from the break of the plane to the ground and continue without altering the path. The whole point is to make the system to be one continuous ground plane.

    There are a lot of techniques to deal with this issue, I can keep on writing pages on the technique I use. That's the reason they have a new category call Signal Integrity engineer that specialize with this issue. I always interested in this and I have been unofficially worked as a signal integrity engineer on and off.

    Back to your original post, if you put capacitors of value 10:1 form say 100uF, 10uF, 1uF, 01, 0.01, 1000pF 100pF and using the ground plane to form a parallel plate capacitor, you are going to get a pretty good ideal capacitor for up to 4 or 5 GHz or beyond.

    Hope this give you a better insight. As I said, I read through only a few pages and the topic is on how to bypass a dense pcb with many voltage in high frequency environment.
    Last edited: Oct 16, 2011
  6. Oct 16, 2011 #5
    May I suggest a book for you on EMC design:

    "High Speed Digital Design, A Handbook of Black Magic" by Howard Johnson. It is 10 years old, manybe there is newer and better book. It is really easy to understand, you don't need EM to understand the book. Together with the paper, you should get a very good understanding about this EMC stuff.
  7. Oct 17, 2011 #6
    Ok, thanks for the tips.
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