What is the Optimal Clock Frequency for a 4029 CMOS Up/Down Counter?

[tenacity2986]

what can be the frequency for the clock signal that is to be counted? I read on another website that it is a minimum of 2MHz! to run optimally...that is. Well I am trying to count heartrate from a microphone that is amplified and filtered to look likea square wave or pulse train...Not sure yet. and it neeeds to display the heart rate in beats per minute and be refreshed every 15 seconds... Hmmm... I understand how i can use the 4011 which is the driver that takes the BCd to 7 segment, yet am unsure how to count the bpm in the backround and send it to the driver every 15 seconds... Please Shed some light thanks. bye

 

[Tom.G]

According to the datasheet here: http://www.ti.com/lit/ds/symlink/cd4029b.pdf

That 2MHz clock is the maximum clock frequency at 5V supply voltage, and goes up to 5.5MHz with a 15V supply. There is not a lower frequency limit, just a requirement that the clock rise and fall times are faster than 15μS.

Cheers,
Tom