Why do we need set up and hold time in Flipflops?
After you apply the input signal it takes some time to charge/discharge the input capacitors. Before that the input nodes will have wrong voltages. Thus set-up time is required to fully prepare the input for sampling.
Flip-flops are bistable devices. However to switch the state you need to drive the gate for a finite time. If your input is short, the output will revert back to the original state. Thus we need hold time to successfully switch the state.
I looked up datasheets of flipflops with same input capacitance but of different family (HC and AC).
The max clock frequency and hence the set up time are different.
74HC73 and 74AC109. Both have 10pf input capacitance for data line. But setup times are different.
The input capacitance sound good when you think of cmos gates. But it's not the same with TTL gates.
its not just capacitance at the input, but the internal capacitors of the intergrated circuit need time to work too
You need certain minimum/maximum voltages at certain internal input nodes (gate node etc.) on the chip at the moment of application of clock. Even if you don't meet that criteria your output will still try to change but before it reaches the desired value it will revert and go back to the initial value. When you have met those criteria you are sure to get the desired output no matter what happens at intermediate time.
Separate names with a comma.