- #1
hoheiho
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- 0
Homework Statement
I am trying to understand a simply CPU which written in system verilog. I understand most of them a part from the red colour part.
Code:
import cpu_defs::*;
module IR [COLOR="Red"](CPU_bus.IR_port bus)[/COLOR];
logic [WORD_W-1:0] instr_reg;
assign [COLOR="red"]bus.[/COLOR]sysbus = [COLOR="red"]bus.[/COLOR]Addr_bus ? {{OP_W{1'b0}},instr_reg[WORD_W-OP_W-1:0]} : 'z ;
always_comb
[COLOR="red"]bus.[/COLOR]op = instr_reg[WORD_W-1:WORD_W-OP_W];
always_ff @ (posedge [COLOR="red"]bus.[/COLOR]clock, negedge [COLOR="red"]bus.[/COLOR]n_reset)
begin
if (![COLOR="red"]bus.[/COLOR]n_reset)
instr_reg <= 0;
else
if ([COLOR="red"]bus.[/COLOR]load_IR)
instr_reg <= [COLOR="red"]bus.[/COLOR]sysbus;
end
endmodule
Normally I will just write it like that, without .bus:
Code:
module IR (input clock, n_reset, Addr_bus, load_IR,
inout sysbus,
output op);
...
..
.
op = instr_reg[WORD_W-1:WORD_W-OP_W];
Why it need .bus in here? Because it has connection with the system bus? In the interface part, it doesn't use any .bus :
Code:
modport IR_port(input clock, n_reset, Addr_bus, load_IR,
inout sysbus,
output op);
Thanks for the help
Ivan
Last edited: