Converting RTL design of computer architecture into REAL Hardware

In summary, the designer wants a schematic of the final computer architecture, which will help them understand how it is implemented into technology-dependent target technology.
  • #1
brainbaby
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TL;DR Summary
Schematic generation and hardware implementation of computer architecture.
Hi guys,

1. Most of the design textbooks which I have seen on computer architecture put stress ONLY till the RTL design of computer architecture. But the story of computer system design goes much beyond the RTL description(i.e how RTL design is converted into actual hardware)

2. We begin from specifications which are entered in form of HDL into the synthesis tools after which a high-level synthesis takes place which converts HDL code into RTL description.I know that RTL design undergoes logic synthesis which generates a gate-level net-list or a logic level circuit that contains logic gates . Now, this logic circuit is mapped into technology-dependent target technology which I think?? compiles those discrete logic gates into an IC package available according to the technology library of the synthesis tool.Lastly, the circuit goes into the physical design phase and fabrication.

Now my interest is the following.

-->I want a complete design example of whole computer architecture which is synthesised from specifications to final technology schematic (as mentioned in pt.2)

-->Please recommend me some resources (book etc. whatever) on computer architecture and organisation which lay heavy stress on hardware implementation part of the design process.

Thanks & Regards
 
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  • #2
brainbaby said:
Summary:: Schematic generation and hardware implementation of computer architecture.

I want a complete design example of whole computer architecture which is synthesised from specifications to final technology schematic (as mentioned in pt.2)
Like this?
 
  • #3
I learned about uPs from this 8080A user's manual, a long time ago. It is a great example of one of the simplest microprocessors. Today the uP systems design is way, way, way more complex. So, you might look for digital design books from the 1970's or so (good news, they're really cheap on the used book sites).

Otherwise, I'd look into studying about state machines. That is where the complexity lies. You'll be disappointed if you dig into how an xor gate is made from nand gates (which is how the real HW does it). It's boring and has more to do with Boolean Algebra than IC design. Once you know how to make a flip-flop and a nand gate you are conceptually done with the modern HW part, the rest is about how things are connected. Of course there are IC designers that spend their careers figuring out how to make a smaller or faster nand gate, or whether they should use nand or nor gates, but that is pretty esoteric and probably not what you want.

In any case, about 40 years ago semiconductor fabrication reached a point where people figured out that designing custom digital structures (like an xor gate) just didn't make sense compared to using lots and lots of optimised basic gates, usually nand gates, IIRC. So the fact is that real world digital synthesis is really about the information content of the design, then someone else's software will map that function onto the standard cells that both maximize density and performance. It's all about the connections between the logic cells, not transistors. The present day culmination of this are things like FPGAs, which are fully generalized and programmable, also huge. The fact is in modern times there really isn't digital hardware as much as there is information, like your RTL code, compiled into a standard programmable logic array, like an FPGA, CPLD, or standard cell ASIC.

The more you dig into this the more boring it gets, IMO. It's all about the information, not the HW implementation inside the IC. BTW, this isn't as true for the interface (I/O) or analog functions of modern microcontrollers.
 
  • #4
I am definitely not an expert; but to me it sounds like you might also want to also read a bit about PDKs.
I think information about some of the TSMC nodes is freely available.
 
  • #5
DaveE said:
It's all about the information, not the HW implementation inside the IC
You got me a little wrong here.
I am not talking bout hardware implementation inside the chip.

My query is about muti-level circuits that contain different ICs and other components interconnected together by a system bus. for eg: computer motherboard.

Let us take this example to make my point clear.
fig: final architecture
FINAL COMPUTER ARCHITECTURE.png
Above is the FINAL computer architecture which I see in probably every other book.
All I want is to implement hardware out of it i.e I want to implement it into a TECHNOLOGY SCHEMATIC.

So what should be my first step??

or you can say that I want to MAP this architecture into TECHNOLOGY HARDWARE.

The sooner I get the technology schematic (bottom figure), I can simulate it into a circuit simulator for eg Altium designer etc.

So the real deal for me is to bridge the gap between this final architecture and its schematic.

fig: schematic (just an e.g- something like this)
TECHNOLOGY SCHEMATIC.png


Note: diagrams are just for demonstration.
 
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  • #6
OK, then I think you'll need to choose a component for each functional block. Then read all of the data sheets to find the details about each signal (something like this). Choose a family of signals and stick with it as much as possible, for example don't try to mix LSTTL and HC logic signals. You'll need to verify that each signal has outputs are compatible with the inputs they are connected to. For example, can a clock driver source enough current for the many inputs it has to drive, etc.

Some functions in your block diagram may no longer be commonly available (things like ALUs etc.) because in the real world they're always integrated as part of a more complex part, like a uP.

It's all about the details of each of the components at that level.

PS: It is also very common for designers now to just replace lots of these basic functions with programmable logic, something like an FPGA or CPLD. This puts you back into the "code is everything" mode.
 
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  • #7
Are you trying to learn how each block works and how to connect them together?
 
  • #8
DaveE said:
OK, then I think you'll need to choose a component for each functional block
Yes, you mean to say it would be a manual mapping of the functional design.
For smaller designs, this method can be acquired. But for high complex circuits a manual procedure would be tiresome, I guess?

for managing complexity, we rely on simulators. However, for direct conversion of functional design into schematic, is any simulator out there? I haven't heard it yet.
 
  • #9
Joshy said:
Are you trying to learn how each block works and how to connect them together?
No, I am looking out for a procedure to convert a functional design into a schematic.
I also need a design example of a smaller design that can be mapped manually as DaveE has mentioned in post #6.
Apart from this if manual mapping can be automated, then which software or simulator can be suitable. At present I am exploring Altium but not sure if it could be possible.

Pls refer my post 5.
 
  • #10
So you want to design what we called back in the 70s a "homebrew computer". Google Homebrew Computer Club, there's probably some PDFs of the magazine around online. I can't remember what the UK equivalent was called, there was a guy at Southampton Uni but I forget his name.

But nobody* hardly anyone has built homebrews or designed MoBos for separate components as a hobby for years, if you are interested in this kind of thing then go and work at Gigabyte or MSI or Adafruit or whatever: as @DaveE says above it just isn't interesting. Not when you can pick up something like this with HDMI and WiFi for the price of a couple of beers.

If you really want to solder something together yourself then how about this for a Raspberry Pi RP2040: https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf

* OK, there are 'special cases' like the guy with 50,000 transistors and breadboards covering half a dozen table tennis tables in the video above.
 
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  • #11
brainbaby said:
for managing complexity, we rely on simulators. However, for direct conversion of functional design into schematic, is any simulator out there? I haven't heard it yet.
In digital systems, it's more like compilers than simulators. That is the beauty of digital, there just isn't any real interaction between the disparate parts. You might simulate a function at the transistor level, for example to see if the adder in the ALU meets it's timing requirements and such. But that simulation would have nothing to do with a memory or I/O function. So, at the system level, simulations wouldn't be related to the HW as much as the SW. Custom ICs may be simulated in their entirety at the transistor level, but I'm not sure that's done so much anymore, with companies favoring a "standard cell" approach.

Even in my mostly analog design career, we never simulated the whole circuit. It wasn't ever worth the effort. You simulate the tricky pieces and assume the normal stuff you've done lots of times will work like it always does.

Still, I'm sure there are "simulators" out there for digital functions. I've used them (a long time ago) as part of CPLD design tools. In those applications they can be good for timing analysis for fast systems since propagation delays depend on the actual mapping of the interconnects inside.
 
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  • #12
So you're meaning something like this? (Courtesy of Altium)

Hierarchical_large_AD18-800x817.png
 
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  • #13
Joshy said:
So you're meaning something like this? (Courtesy of Altium)
Somewhat yes. Though the image is bit blurry, it seems that the top fig is a block design that seems to be converted into a much simpler abstraction (not sure)
or we can say that it's an eg of project hierarchy where each schematic document is linked back to the top sheet.

Well the above is somewhere near to my expectations but this I think is an example of encapsulation (i.e wrapping up of data into a single unit (just like blocks here))

This is NOT synthesis

I want synthesis i.e breaking a larger hierarchy into a much simpler one with the use of CAD tools or manually but for a smaller design, as I've iterated earlier.


As, synthesis starts with specification. Then those specs are entered via an HDL code into the compiler
The code is then converted into Dataflow graph (all this as a part of High Level Synthesis)
or it can be said that specification can also be entered in the form of optimised CDFG into the synthesis tool. RTL design is the output of high level synthesis which is further required for logic level synthesis.
 
  • #14
brainbaby said:
I want synthesis i.e breaking a larger hierarchy into a much simpler one with the use of CAD tools or manually but for a smaller design, as I've iterated earlier.
I think automated synthesis really only works for simple functions or highly constrained HW. Often the work of a designer requires background knowledge in related fields, detailed knowledge of what's been done (i.e. theft, LOL), and a bit of creativity. I'm not sure we can tell you how to design the next great circuit or system. Anyway, I can't.

Sometimes the system specification is, defacto, the synthesis. I think this may be required for automation. Writing a really good specification is really hard. A more general set of requirements will require some interpretation from the designer.
 
  • #15
I don't think the tool you're looing for exists, or if it does, then it's very limited or unreliable.
 

1. How do you convert RTL design into actual hardware?

The conversion process involves several steps such as synthesis, place and route, and timing analysis. Firstly, the RTL code is synthesized into a gate-level netlist. Then, the netlist is mapped onto the target hardware, and the physical placement of the gates is determined. Finally, timing analysis is performed to ensure that the design meets timing constraints.

2. What are the challenges involved in converting RTL design into hardware?

The main challenges include ensuring the design meets timing constraints, optimizing for power and area, and debugging any errors in the design. Additionally, the complexity of the design and the target hardware can also pose challenges.

3. What is the role of a hardware description language in the conversion process?

A hardware description language (HDL) is used to describe the behavior and structure of a digital circuit. It is used to write the RTL code, which is then used for synthesis and other conversion processes. HDLs, such as Verilog and VHDL, allow for efficient and accurate representation of the design.

4. How is the functionality of the RTL design verified in the conversion process?

Functional verification is an important step in the conversion process to ensure that the hardware implementation matches the intended behavior described in the RTL code. This is typically done through simulation, where test vectors are applied to the design and the results are compared to the expected outputs.

5. What are some tools commonly used for converting RTL design into hardware?

There are several tools available for converting RTL design into hardware, such as synthesis tools like Synopsys Design Compiler and place and route tools like Cadence Encounter. Additionally, simulation tools like ModelSim can be used for functional verification. These tools help in automating the conversion process and optimizing the design for power and area.

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