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Homework Statement
This question has several parts, and I'm confused about some of them.
Consider ##Z = \overline{(A + B \bar{C})D + E \bar{F}}##. Assume primary and inverted inputs are available.
A) Implement the function in conventional CMOS logic style such that only 4 transistors are connected to the output node, and the PMOS and NMOS transistors with input "A" are attached to ##V_{DD}## and ground (by their source), respectively. Assume all PMOS have ##W/L = 15## and all NMOS have ##W/L = 6##. Place a ##50 fF## load capacitance at the output.
B) and C) I had no problem with.
D) Calculate the worst-case rising and falling propagation delays. Only consider the load capacitance and ignore the internal capacitances.
E) No problem.
F) Calculate the best-case rising and falling propagation delays. Only consider the load capacitance and ignore the internal capacitances.
G) Design the same circuit for equal rising and falling delays of ##100 ps##. Provide two sizing solutions and indicate ##W/L## of the transistors on the circuit. Identify the better solution with a reason.
Homework Equations
##D_r = \frac{C_L V_{DD}}{2 I_P}##
##D_f = \frac{C_L V_{DD}}{2 I_N}##
The Attempt at a Solution
Here is my work so far:
I want to know if my answer to part A) looks okay.
I know the answers to B) and C) are correct.
D) To find the worst case delay, I have to consider the longest critical path or something along those lines. I am unsure how to do this question.
E) This question is doable if I can solve D) and so I won't need to talk about it.
F) The best case delay means all the paths are active at the same time. I am still unsure.
G) I will get to this.
If part A) looks okay, I need some help with part D).
Thank you.