Recent content by dafaq

Thanks. I also believe that there should be a way to do that considering Cadence being a big name. The biggest challenge is there is no tutorial anywhere regarding that matter! I am not so familiar with this forum, do you know if I can tag someone for any help?

Hi, I'm currently using cadence virtuoso to design circuit for all-spin-logic device (a kind of spintronics devices). I found in a paper "Circuit Simulation of Magnetization Dynamics and Spin Transport" by Phillip Bonhomme etc. that it can be done using the circuit as follows: They...

umm..here is what i found in my textbook..have a look.. it says dual rail domino cannot have both inputs high at the same time... check the image i attached along as pdf (just change the extension to .jpg from .pdf) and see the table... if i take that for granted then i believe the circuit is...

:cry: but how do i find that ! for two inputs i already have used all possible 4 combination vectors.. T_T i have no clue how to find the state u r talking.. i do understand theoritically what u r saying but no clue how to get that practically... :(

? " However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high." ---> i see only one situation when both are 1 ! Y & Y' being 1 and 0 respectively... -_- what am i missing.. T_T

hellowwww :) here i am again ^_^ with doubts... (as always) please have a look at the circuit , it is i believe a dual rail domino gate, i want to determine the output Y and Y'.. i used hspice to be sure that i didn't make any silly mistake. here is the hspice output in cscope.. (i used vector...

yep..labeling did help a lot...without labels it is very tough to read the layout (almost impossible) ... i stuck to ur advices till the end and i was finally able to make things right.. thank u so much ^_^ and yep, i got rid of those poly, i didnt like them anyway, previously i used them just...

hi, i was a bit busy with all these so couldn't reply sooner, i figured the problem and fixed it. i had to use separate pin instead of using explicit vdd and gnd instances. here is my final layout, have a look and say if it looks good or not :) i am attaching the jpg with changed extension as...

http://tinypic.com/r/2me3fbc/5 what are the meaning of these ! :(

do u have any idea why it is saying "power net missing in source" ? the first error right under the incorrect sign!

so, should i use labels instead of wires to draw the schematic?

this is the new lvs error report http://tinypic.com/r/2cen2ao/5 have a look please

i fixed the number of ports.. actually i directly connected outputs of the inverts in the schematic ! so when i specified the inverter's output ports they threw errors.. i have a different error now.. i will upload the lvs report 1 min please

whoao.. now that's interesting ! let me see.. -_- dont go anywhere ! :)

here it is http://tinypic.com/r/ofzvc6/5