How to understand design layout (VLSI)

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The discussion focuses on understanding the layout of an SR NOR latch in CMOS design. Participants emphasize the importance of tracing the layout to match it with the schematic, highlighting the use of color coding for different components. They recommend using Cadence for design entry, noting its steep learning curve but extensive capabilities. Questions arise about the necessary background in digital electronics for layout design, with responses indicating that practical experience is often more valuable than formal education. Finally, a query about analyzing a 2:1 multiplexer leads to insights on delay and power consumption based on input patterns, stressing the significance of signal paths in determining performance.
  • #51
so, should i use labels instead of wires to draw the schematic?
 
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  • #52
No, it's fine the way it is. I'm just saying that you can add labels to the internal nodes on your schematic and on your layout, and then when there is a port missing, you know which one is missing without having to look through the entire thing trying to figure it out.
 
  • #53
do u have any idea why it is saying "power net missing in source" ? the first error right under the incorrect sign!
 
  • #55
Sorry, I don't know enough about your LVS tool to know the answer. It seems to not find the power net in the schematic, but it appears to be there. Perhaps you need a specific label on Vdd and Vss? Try reading the LVS manual.
 
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  • #56
hi,
i was a bit busy with all these so couldn't reply sooner, i figured the problem and fixed it. i had to use separate pin instead of using explicit vdd and gnd instances. here is my final layout, have a look and say if it looks good or not :)
i am attaching the jpg with changed extension as pdf. download it and change the pdf format to jpg and it will be good enough :)
thanks for ur help... ^_^
 

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  • #57
Congratulations on sticking with it until it passed. It looks OK to me. I see you got rid of those long poly runs, which are resistive and will slow things down. I see you also now have everything labeled. Did the labeling help with deciphering the LVS output?
 
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  • #58
yep..labeling did help a lot...without labels it is very tough to read the layout (almost impossible) ... i stuck to ur advices till the end and i was finally able to make things right.. thank u so much ^_^ and yep, i got rid of those poly, i didnt like them anyway, previously i used them just because i didnt have enough room to route my signals separately.. :)
 
  • #59
hellowwww :)
here i am again ^_^ with doubts... (as always)
please have a look at the circuit , it is i believe a dual rail domino gate, i want to determine the output Y and Y'.. i used hspice to be sure that i didn't make any silly mistake. here is the hspice output in cscope.. (i used vector file to give inputs to A and B and the input vectors of A and B are like - 00,01,10,11,00,00,00,01,10,11,)
now, the truth table of this compound gate is -

A B Y Y'
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 0

i am a bit confused what logic it actually implements... the Y is always equal to A, and Y' is equal to B for first 3 inputs.. can u please throw some insight ? :)
 

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  • #60
I'm not sure exactly what it is either, but your analysis is incomplete. If A and B are both low, then Y and Y' are both low as you have it. However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high. It is not simply a combinational logic circuit - because of the internal feedback it can store data from the past history as well.
 
  • #61
? " However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high." ---> i see only one situation when both are 1 ! Y & Y' being 1 and 0 respectively... -_-
what am i missing.. T_T
 
  • #62
dafaq said:
? " However, when A and B are both high, there are two stable states, one with Y high and Y' low, and one with Y low and Y' high." ---> i see only one situation when both are 1 ! Y & Y' being 1 and 0 respectively... -_-
what am i missing.. T_T

Isn't it completely left/right symmetric? If there is a state with Y high and Y' low, doesn't there have to be a corresponding state with Y low and Y' high?
 
  • #63
:cry: but how do i find that ! for two inputs i already have used all possible 4 combination vectors.. T_T i have no clue how to find the state u r talking.. i do understand theoritically what u r saying but no clue how to get that practically... :(
 
  • #64
dafaq said:
:cry: but how do i find that ! for two inputs i already have used all possible 4 combination vectors.. T_T i have no clue how to find the state u r talking.. i do understand theoritically what u r saying but no clue how to get that practically... :(

You need to force the simulator into the correct state by introducing some left/right asymmetry. Try adding a small capacitor to one of the two cross-coupled gates (the gates of the middle NMOS devices). With the capacitor on the left it should go one way, and with the capacitor on the right it should go the other way.
 
  • #65
phyzguy said:
You need to force the simulator into the correct state by introducing some left/right asymmetry. Try adding a small capacitor to one of the two cross-coupled gates (the gates of the middle NMOS devices). With the capacitor on the left it should go one way, and with the capacitor on the right it should go the other way.

umm..here is what i found in my textbook..have a look.. it says dual rail domino cannot have both inputs high at the same time... check the image i attached along as pdf (just change the extension to .jpg from .pdf) and see the table... if i take that for granted then i believe the circuit is kind of like multiplexer... Y always follows A and Y' follows B... what do u say?
 

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