Recent content by Lanot

Actually, I just realized that this circuit lacks the async preset/clear functions. EDIT: I just learned about this circuit: http://en.wikipedia.org/wiki/Flip-flop_(electronics)#Edge-triggered_dynamic_D_storage_element That probably works. Thank you guys.

Wow, that's really impressive. I'll see if it works. Yeah, The point here is that I don't care about the FF design right now, I just need it to be as fast as possible for characterization purposes. Thank you.

Not building exactly, just designing. I'm free to use custom flip-flops. I just used the ones that the paper suggested. Take a look at: http://ipnpr.jpl.nasa.gov/progress_report2/XIII/XIIIW.PDF p. 5 shows the classical approach with D flip flops and p. 9 shows the alternative one with JK FFs

Like I said before (in other words), the good old 7474 ( http://home.gwi.net/~pstewart/7474diag.gif ) uses 6 nand3 gates (which in cmos would require 36 transistors). For the design I'm using, despite the higher number of transistors/flip-flop, it's still a better trade-off in terms of...

It's an old design for a control logic of an ADC. It was proposed on 1972. They proposed a version using D flip flops, which uses 2N+2 DFFs and a version with JK with N+1 FFs. Of course it was targeted to LSI/MSI applications. I did some calculations, and found out that the JK version...

Hi guys, I'm simulating a circuit which uses a few (actually, 10) Positive-Edge-Triggered JK flip flops. The exact flip-flop design that I'm using is the SN7476 from TI. I need a flip-flop like this, since I need Preset and Clear asynchronous inputs. The datasheet is as follows...

Sorry for the delay. Now I can see the transient response. But the curve doesn't seem right I guess. The code is: Vin vin 0 DC 0 pulse=(0 1.2 0 50n 0 0 0 0 51n) Vac vin vr1 AC 0 SIN (0 10m 100MEG) R1 vr1 v2 100k M1 0 v2 0 0 nmos l=1 w=10 .TRAN 1p 50n .end The response is as follows:

No, I can't. Isn't it because it's a DC sweep analysis? The code is as follow: Vin vin 0 DC 1 Vin vin 0 Vac vin vr1 AC 1 SIN (0 1 100MEG) R1 vr1 v2 100k M1 0 v2 0 0 nmos l=1 w=10 .DC SWEEP vin -1 3 1m .end

I forgot to tell. I tested the circuit with a capacitor, and the current is zero.

Unfortunately, I couldn't replicate this experiment. I don't know what's the problem. I was able to obtain an estimate of the MOS capacitance with a .op simulation (cgtot parameter), for low frequencies. The only thing that is missing is the high frequency behavior of the moscap.

Nothing changed. Vin vin 0 Vac vin vr1 AC 1 SIN (0 1 0.159) R1 vr1 v2 1k M1 0 v2 0 0 nmos l=1 w=10 .DC SWEEP vin -1 3 1m .end

Do you mean a DC sweep like this? Vin vin 0 AC 1 SIN (0 1 0.159) R1 vin v2 1k M1 0 v2 0 0 nmos l=1 w=10 .DC SWEEP vin -1 3 1m .end The current is zero though.

Hi guys, I'm trying to obtain the CxV curve from moscap in SPICE (hspice). Note that I'm not talking about the sum of the capacitances from the mos transistor, but the transistor behaving as a capacitor. Is there an easy way to do this?

Yes, you are correct. The signal in question may swing from ground to vdd though. So isn't there a better approach?

Hi guys, Recently I had to design a SPDT switch for a project, which I was able to design using the trivial circuit with 2 transmission gates and 1 MOS inverter, like this: http://www.semicon.toshiba.co.jp/eng/product/new_products/logic/1326183_37648.html I think that this circuit is not...