SPDT switches in CMOS processes.

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The discussion centers on designing a Single Pole Double Throw (SPDT) switch using CMOS processes. The initial design employs two transmission gates and a MOS inverter, but concerns are raised about the introduction of parasitics from multiple switches. Alternatives are suggested, such as using two N-channel FETs for specific grounding applications, depending on the switching requirements. The effectiveness of the circuit is contingent on the specific signal characteristics, particularly if the signal swings between ground and VDD. A schematic of the proposed design would facilitate a more tailored solution.
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Hi guys,

Recently I had to design a SPDT switch for a project, which I was able to design using the trivial circuit with 2 transmission gates and 1 MOS inverter, like this: http://www.semicon.toshiba.co.jp/eng/product/new_products/logic/1326183_37648.html

I think that this circuit is not optimal, since it introduces the parasitics from two switches.
The question is: Is there a better circuit to do this?

Thank you.
 
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That is optimal if you want bi-directional switching of arbitrary signals between VDD and VSS.

If you switching requirements are different, you may get away with two fets. For example if all you want to do is ground 1 line or the other you can use 2 N channel FETs to ground. etc etc etc

It depends on exactly you are trying to do.
 
Yes, you are correct.
The signal in question may swing from ground to vdd though. So isn't there a better approach?
 
Again, it depends on exactly what you are doing. A schematic would help.
 
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