SPDT switches in CMOS processes.

[Lanot]

Hi guys,

Recently I had to design a SPDT switch for a project, which I was able to design using the trivial circuit with 2 transmission gates and 1 MOS inverter, like this: http://www.semicon.toshiba.co.jp/eng/product/new_products/logic/1326183_37648.html

I think that this circuit is not optimal, since it introduces the parasitics from two switches.
The question is: Is there a better circuit to do this?

Thank you.

 

[meBigGuy]

That is optimal if you want bi-directional switching of arbitrary signals between VDD and VSS.

If you switching requirements are different, you may get away with two fets. For example if all you want to do is ground 1 line or the other you can use 2 N channel FETs to ground. etc etc etc

It depends on exactly you are trying to do.

 

[Lanot]

Yes, you are correct.
The signal in question may swing from ground to vdd though. So isn't there a better approach?

 

[meBigGuy]

Again, it depends on exactly what you are doing. A schematic would help.

 

[alphy]

I can tell you that there are indeed better circuits for designing SPDT switches in CMOS processes. One alternative is to use a cross-coupled inverter topology, which can provide improved performance and reduced parasitics compared to the circuit you mentioned. Additionally, there are various techniques and design considerations that can be used to optimize the performance of SPDT switches, such as minimizing leakage current and improving isolation between the two paths. It is always important to carefully consider the specific requirements and constraints of your project when selecting a circuit design. I suggest exploring different options and consulting with other experts in the field to determine the best approach for your specific application.