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SPDT switches in CMOS processes.

  1. Feb 8, 2014 #1
    Hi guys,

    Recently I had to design a SPDT switch for a project, which I was able to design using the trivial circuit with 2 transmission gates and 1 MOS inverter, like this: http://www.semicon.toshiba.co.jp/eng/product/new_products/logic/1326183_37648.html

    I think that this circuit is not optimal, since it introduces the parasitics from two switches.
    The question is: Is there a better circuit to do this?

    Thank you.
     
  2. jcsd
  3. Feb 8, 2014 #2

    meBigGuy

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    Gold Member

    That is optimal if you want bi-directional switching of arbitrary signals between VDD and VSS.

    If you switching requirements are different, you may get away with two fets. For example if all you want to do is ground 1 line or the other you can use 2 N channel FETs to ground. etc etc etc

    It depends on exactly you are trying to do.
     
  4. Feb 8, 2014 #3
    Yes, you are correct.
    The signal in question may swing from ground to vdd though. So isn't there a better approach?
     
  5. Feb 8, 2014 #4

    meBigGuy

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    Gold Member

    Again, it depends on exactly what you are doing. A schematic would help.
     
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