Recent content by Max0007

Homework Statement I work on Microsoft Visual studio 2010 on Win7. Ok so let me explain the problem here, The functions works very good to position my printf in X and Y on my screen ONLY when my 2D Array labyrinth Map is NOT printed on the screen. But once I printf my Map on the screen I...

Time B - Time A? only that :O

"Which way was the ball thrown from the top? (Same problem in part b.)" downward so its -2.5m/s But for part b) I realized I did not do the right thing. I don't know how to actually do it ;(

Homework Statement The top of a 10-storey building (42 m) , someone throws a ball (A) down with a initial speed of 2.5 m / s. You are on the second floor (8 m window above the ground) and You throw a ball (B) upward with an initial speed of 22 m / s. a) If both balls are thrown together after...

so in my point of view if I have x=1 and other input to 0 then bout(1)/bout(0) would take the value of 01 = which means 1 bit detected. aout(1)/aout(0) would also take the value of 01. a serial stream of bits (going in on 1 wire)

Yes but I am checking from right to left and left to right. So I only have to check for 2 bits from right to left and 2 bits from left to right and Xi is what my current cell value is = fifth bit.

Better now ?

Yes

Well I would have 16 cells like the one I draw. And my circuit would receive a sequence of 16 bits at a time.

Homework Statement I have to detect a pattern (11011) once this detected I put a 1 in my ouput Z to 1 to the 0 of the pattern. Example : 11011001... 00100000... Homework EquationsThe Attempt at a Solution

Homework Statement I have a quick question here, Since I have s_o(o) and s_o(1) do I do 2 table of truth for those or mix both and do one table of truth? the (1)/(0 ) are confusing me. Homework Equations w_o <= not d_i and (b_i(1) or d_i); s_o(0) <= d_i or b_i(1); s_o(1) <= not b_i(0) and...

Nice awesome thanks. I really learn a lot more here than in Class at the University so far. :)

how would I calculate it if I had 3 different gates in parallels?

2+5= 7 then I

one last thing :) If an inverter has a 2 ns propagation delay , an AND logic gate has a 5 ns propagation delay and an OR gate has a 4ns delay , what is the maximum period required by the circuit in order to update the output F ? would I just do 2ns x 2 sicne I have 2 inverter and 5ns x1 since...