VHDL equations to table of truth

[Max0007]

Homework Statement

I have a quick question here,
Since I have s_o(o) and s_o(1) do I do 2 table of truth for those or mix both and do one table of truth?

the (1)/(0 ) are confusing me.

Homework Equations

w_o <= not d_i and (b_i(1) or d_i);

s_o(0) <= d_i or b_i(1);

s_o(1) <= not b_i(0) and d_i;

The Attempt at a Solution

Thank you very much and sorry for asking so much questions lately :)

 

[lewando]

If you are generating a truth table to document the behavior of one or more outputs as a function of some inputs, then one truth table with multiple outputs is commonly done. If your question is how best to implement a "truth table"-like description in VHDL, I have only seen single-output constructs using a WITH-SELECT or PROCESS statement.

s_o(1) and s_o(0) look like the 2 least significant bits of a variable s_o, a "bit_vector" type --probably the outputs that you are interested in defining.