1. Not finding help here? Sign up for a free 30min tutor trial with Chegg Tutors
    Dismiss Notice
Dismiss Notice
Join Physics Forums Today!
The friendliest, high quality science and math community on the planet! Everyone who loves science is here!

VHDL equations to table of truth

  1. Feb 15, 2015 #1
    1. The problem statement, all variables and given/known data
    I have a quick question here,
    Since I have s_o(o) and s_o(1) do I do 2 table of truth for those or mix both and do one table of truth?

    the (1)/(0 ) are confusing me.

    2. Relevant equations

    w_o <= not d_i and (b_i(1) or d_i);

    s_o(0) <= d_i or b_i(1);

    s_o(1) <= not b_i(0) and d_i;
    3. The attempt at a solution


    Thank you very much and sorry for asking so much questions lately :)
     
  2. jcsd
  3. Feb 16, 2015 #2

    lewando

    User Avatar
    Gold Member

    If you are generating a truth table to document the behavior of one or more outputs as a function of some inputs, then one truth table with multiple outputs is commonly done. If your question is how best to implement a "truth table"-like description in VHDL, I have only seen single-output constructs using a WITH-SELECT or PROCESS statement.

    s_o(1) and s_o(0) look like the 2 least significant bits of a variable s_o, a "bit_vector" type --probably the outputs that you are interested in defining.
     
Know someone interested in this topic? Share this thread via Reddit, Google+, Twitter, or Facebook

Have something to add?
Draft saved Draft deleted



Similar Discussions: VHDL equations to table of truth
  1. Truth Table (Replies: 2)

Loading...