Understanding the Master & Slave Roles in IIC Bus Technology

AI Thread Summary
In IIC Bus technology, the master is the controller that manages communication and dictates when data is transmitted, while slaves are the devices that respond to the master's commands. Each slave has a unique address that the master uses to communicate, ensuring that only the addressed slave responds to a command. The master sends a slave address immediately after a START signal, and only the slave with the matching address acknowledges the communication. In scenarios with multiple masters, arbitration occurs to determine which master controls the bus at any given time. Understanding these roles is crucial for grasping how data is transferred effectively on the IIC Bus.
seang
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Hey all;

I have to write a report on a certain bus (the bus is associated with a uC), based on a technical document. Thing is, we haven't learned much about buses yet. I understand most of it, but there's one thing I don't understand.

What is a slave and what is a master? Here's some phrases from the doc. I think If someone could explain them I'd have a lot better handle on buses and the master/slave idea in general.

"This register contains the address the IIC Bus will respond to when addressed as a slave."

"This would ultimately result in either the current bus master or the IIC Bus module losing arbitration..."

(the IIC is the name of the bus)

"IAAS — Addressed as a slave bit"

"0 = Slave receive, master writing to slave
1 = Slave transmit, master reading from slave"

"The first byte of data transfer immediately after the START signal is the slave address transmitted by the master."

"Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit."

Thanks.
 
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The bus is just the medium for transferring data between units. The Bus type defines the architecture and the signal types that can be used on the data wires.
Master Slave Buses use a single Bus Controller (The Master) to control what and when information is transmitted on the bus. this prevents two units talking at the same time (Data Collision).

The Bus Controller will talk to every slave unit on the bus, but only the one which matches the address in the message header will respond to the command. The Bus controller will then wait to receive the response before sending out the next command. Generally Slave units cannot transmit unless directly commanded by the Master.

"This register contains the address the IIC Bus will respond to when addressed as a slave."

The slave stores a unique address which the Master can use to talk to it. Depending on Bus type this address can be fixed or dynamic and the master can either be preprogrammed with slave addresses or request an address.

"This would ultimately result in either the current bus master or the IIC Bus module losing arbitration..."
I assume this is where you have the possiblility of multiple Bus Masters on a single Bus. A single Bus Master will controll all other devices as slaves, but under certain circumstances another Bus Master may take control of the Bus. The Bus Master is arbitrating between units to determine which unit communicates.

"IAAS — Addressed as a slave bit"

"0 = Slave receive, master writing to slave
1 = Slave transmit, master reading from slave"
This is referring to information within the message header for a serial bus or on a specific line for a parallel bus to indicate which direction data is flowing in.

"The first byte of data transfer immediately after the START signal is the slave address transmitted by the master."
If this is in a dynamically addressed system the Master is telling slaves what addresses it wants to operate on and also finding out how many slaves are on the network. Otherwise it is referring to the fact that each message frame header begins with a start of message pattern and is then followed by the address of the slave unit the message is for.

"Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit."
Any other slave unit will hear the message but as the address will not match it's own it will ignore the instruction.
 
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