AC Hipot Test on MOSFET: Can It Be Done?

[newengr]

TL;DR

I would like to do an AC hipot test on a board with a MOSFET

Hi,

I have a test board that I would like to do an AC hipot test on a MOSFET with connections across the drain/source. Since because of the built in diode, current flows during the negative half cycle. Is AC hipot possible for a MOSFET, or is DC required?

 

[DaveE]

All will be OK provided you don't ever exceed any of the Absolute Maximum Specifications on the data sheet.
Otherwise it's hard to answer without more detail, like a schematic and a description of what/how/why your testing.

 

[newengr]

All will be OK provided you don't ever exceed any of the Absolute Maximum Specifications on the data sheet.

Sorry, I should have provided more details. The hipot is connected with the HV excitation to the drain and GND to the source. The excitation is 60 Hz AC. During the positive half cycle, the device is off so it is blocking. The body diode is basically an antiparallel diode so it is reverse biased. During the negative half cycle of the excitation, the body diode is now forward biased so current will flow. The problem is twofold. 1) I'm expecting no (low) leakage current since this is an insulation test. 2) On top of the current flow that should not happen, the magnitude of the current is larger than the current limit of my supply. It's a hipot so no need for a high current rating.

 

[berkeman]

Summary:: I would like to do an AC hipot test on a board with a MOSFET

Hi,

I have a test board that I would like to do an AC hipot test on a MOSFET with connections across the drain/source. Since because of the built in diode, current flows during the negative half cycle. Is AC hipot possible for a MOSFET, or is DC required?

Can you say more about why you are wanting to do a HiPot test on this device/board? What AC voltage are you wanting to achieve? What kind of device are you planning on using this MOSFET in, and why would it be exposed to a HiPot test? Is the HiPot test just part of design validation, or will it be used in production of some device?

 

[DaveE]

That's a really odd test requirement. Is this for a product safety standard? You're the first person I've ever heard propose an active semiconductor device as insulation. This sounds more like a curve tracer or avalanche breakdown test to me.

Anyway, a normal Hi-Pot test will require a delay of greater than 10msec so an AC test will fail because of the anti-parallel diode, as you say. You'll need to use DC. This is what you would want anyway, since the test voltage should mimic the voltage stress in normal/abnormal operation, but at a higher value.

OTOH, since this test doesn't match my experience for why it's required, I'm also not sure how it should be done.

 

[anorlunda]

This article discusses some details of hipot testing. More importantly, it mentions several IEC standards for hipot testing of different kinds of equipment. Your questions can't be answered without reference to the applicable standard.

https://www.electronicsweekly.com/n...ing-hi-pot-testing-and-its-standards-2012-08/

 

[DaveE]

I don't think this is about the common IEC product safety standards (like EN60950, EN601010, EN60204,...). At least 15 years ago when I last did this stuff (a lot), those inspectors would have broke out in uproarious laughter if you proposed using a MOSFET as insulation for safety. They wouldn't care about the result, you'd fail anyway*. Hi-Pot testing isn't enough, there are also materials and construction standards. Something else is going on here. Some other meaning of Hi-Pot.

*OK, really, you'd have to hire the expensive gurus, argue a lot, put forth a comprehensive case study to prove safety, and conduct a difficult testing program. Then you'd probably fail, but maybe not. This rarely happens because it's cheaper to redesign your product. The time to market cost combined with the risk of failure is extreme. Smart designers do things the normal way.

 

[newengr]

That's a really odd test requirement. Is this for a product safety standard? You're the first person I've ever heard propose an active semiconductor device as insulation. This sounds more like a curve tracer or avalanche breakdown test to me.

Anyway, a normal Hi-Pot test will require a delay of greater than 10msec so an AC test will fail because of the anti-parallel diode, as you say. You'll need to use DC. This is what you would want anyway, since the test voltage should mimic the voltage stress in normal/abnormal operation, but at a higher value.

OTOH, since this test doesn't match my experience for why it's required, I'm also not sure how it should be done.

This is just for experimental purposes, nothing production. I'm not wanting to test the device insulation but the board and footprint. If it was device then I would definitely use a curve tracer. I know there are IPC standards for minimum creepage/clearance or I can encapsulate the device if I'm not able to meet them. I was just curious about the performance before potting. Performance with the device installed will be different than just testing the board alone so I was hoping there was a clever way to do it like this. Even if the device will not be operating under AC, it's easier to spot out partial discharge under AC than it is DC. It looks like DC hipot it is.

 

[berkeman]

I'm not wanting to test the device insulation but the board and footprint.

HiPot testing is not for devices. It is for testing mechanical arrangements of products to be sure that the insulation between AC Mains input and user-accessible metal is sufficient to not lead to dangerous arc-over.

Who gave you the advice to HiPot test this MOSFET?

https://en.wikipedia.org/wiki/Dielectric_withstand_test

 

[DaveE]

This is just for experimental purposes, nothing production. I'm not wanting to test the device insulation but the board and footprint. If it was device then I would definitely use a curve tracer. I know there are IPC standards for minimum creepage/clearance or I can encapsulate the device if I'm not able to meet them. I was just curious about the performance before potting. Performance with the device installed will be different than just testing the board alone so I was hoping there was a clever way to do it like this. Even if the device will not be operating under AC, it's easier to spot out partial discharge under AC than it is DC. It looks like DC hipot it is.

OK, got it. You don't actually care what happens to the MOSFET. It's really a test of the exposed conductors (traces, heatsink tabs, etc.). Then you problem now is to tell the difference between internal conduction, which you don't care about, and an external "flash-over". One option would be to use a different device in the same package, like a HV diode.

I'm not at all sure what evaluation of arcing through air will tell you about the encapsulated version. Arcing along surfaces (creepage) is applicable if you have poor design or production of the encapsulation steps. We used to always assume that the encapsulant wouldn't bond well, or maintain a bond with aging, across dissimilar materials (surfaces) and that the creepage standards still apply as if there was not encapsulant. That's why you will often see slots cut out of HV PCBs that are later encapsulated; to increase the creepage paths around the encapsulant.

I'm not sure the creepage paths are really changed much by adding devices. They are normally adding metal above the board but still leave the shortest path from trace to trace at the PCB level. But I have no idea about your geometry.

 

[newengr]

HiPot testing is not for devices. It is for testing mechanical arrangements of products to be sure that the insulation between AC Mains input and user-accessible metal is sufficient to not lead to dangerous arc-over.

Who gave you the advice to HiPot test this MOSFET?

https://en.wikipedia.org/wiki/Dielectric_withstand_test

I'm not wanting to HiPot test the device. I'm wanting to HiPot with my board with the device installed. If I wanted to test the device, I would use a curve tracer. I understand that HiPot is for insulation testing. The insulation performance of the board will be different than the insulation performance of the assembly. I was trying to get a better understanding of the assembly insulation performance before potting.

 

[newengr]

OK, got it. You don't actually care what happens to the MOSFET. It's really a test of the exposed conductors (traces, heatsink tabs, etc.). Then you problem now is to tell the difference between internal conduction, which you don't care about, and an external "flash-over". One option would be to use a different device in the same package, like a HV diode.

I'm not at all sure what evaluation of arcing through air will tell you about the encapsulated version. Arcing along surfaces (creepage) is applicable if you have poor design or production of the encapsulation steps. We used to always assume that the encapsulant wouldn't bond well, or maintain a bond with aging, across dissimilar materials (surfaces) and that the creepage standards still apply as if there was not encapsulant. That's why you will often see slots cut out of HV PCBs that are later encapsulated; to increase the creepage paths around the encapsulant.

I'm not sure the creepage paths are really changed much by adding devices. They are normally adding metal above the board but still leave the shortest path from trace to trace at the PCB level. But I have no idea about your geometry.

Yes, that's correct; the problem is the device conduction. The diode within the MOSFET is actually the problem because I'm using AC. During the positive half cycle of the excitation, Vds is positive. The MOSFET is blocking and the body diode of the device (basically an antiparallel diode) is reversed biased so there is negligible current. During the negative half cycle of the excitation, Vds is negative. The MOSFET is still blocking but the body diode is now forward biased. The conduction current through the body diode is 1) not wanted and 2) exceeds my HiPot current limit. So I was trying to figure out a way to get around this.

I think I would have the exact same problem with a HV diode since the body diode is my problem. Your suggestion about getting a HV diode with the same package might still be helpful though. I would need a small valued capacitor (not likely to exist) or a very large enough value resistor. I'm doubtful I'll find a resistor in that package of the value I need for insulation testing, but I think that may be the only option at this point.

I wouldn't expect arching through air on the potted version. Basically, I was wanting to measure the partial discharge inception voltage (PDIV) of the version in air to quantify the increase the increase in insulation performance by encapsulating. Thanks for the explanation about the slots for creepage, I'll make sure to include those as well.

You're correct in this case about the device not changing the creepage distance. It does change the shape of the e-field in that region, which is a critical region. I can add round corners to pads to reduce peak field intensity but if I go and add a device with sharp corners on the pins then I'll increase the peak e-field intensity increasing the likelihood for of flashover OR even just corona. So I think it would be beneficial to evaluate boards with and without devices installed...just doesn't seem to be possible in this case.

 

[DaveE]

You're correct in this case about the device not changing the creepage distance. It does change the shape of the e-field in that region, which is a critical region.

So will the encapsulant.

The key issue with partial discharge in encapsulated system is to avoid any discontinuities in the insulation, especially if they are voids. If you think partial discharge is and issue then you'll want to do vacuum impregnation and avoid materials that won't bond well with the encapsulant.

While it probably doesn't apply for a PCB, a common mistake here is for people to use films like kapton instead of more porous things like fiberglass. This tends to create voids at the interstitial boundaries. Partly because it impedes evacuation and refilling with insulation, and partly because the encapsulant doesn't bond to the film. In a PCB this may apply to solder mask layers, for example (although that is kind of paranoid).

There are a couple of ideas I might consider. Depending on the device package, I might just take a chisel or saw to it and physically remove the non-metal bits before your test. You could also try destroying the internal device with high current, although this is likely to leave conductive bits inside and might not tolerate HV, you could test the device alone before you install it to see if you've really neutered it.

What peak voltages are you working with?

 

[newengr]

Ah I like the idea about frying it. It's at least worth a shot. Even cutting the device with a saw may work, gap would need to be large enough so that I don't see corona there which may be hard. It's still worth a shot though. I'm hoping for the high current to fry it though because that would give me the closest result to what I should actually see in the setup.

Thanks for the tips on encapsulant. I know it's not the total solution, but I may use a light grit sand paper before encapsulating to add a bit more surface roughness and see if he helps with bonding (there are no traces directly beneath).

The peak voltage is 1.5 kV but it's on a rather small package. I'll have to find the part number but it will definitely not be possible to meet IPC standard for creepage or clearance without slots and encapsulant. I just want to see exactly where the PDIV is in air and what it increases to with encapsulant. I'll definitely be doing VPI.

 

[DaveE]

1.5KV should be easy with good encapsulation. I don't think you have to do anything special or difficult. Partial discharge isn't a big issue at those voltages. The one thing you'll want to do is encapsulate to eliminate voids with oxygen. PD can turn O₂ into O₃ which will degrade insulation with time.

Really, you can't have assemblers sanding your circuit. They'll do it wrong. They'll break things (like ESD). They will cost a lot of money. That shouldn't be necessary for 1.5KV. Design insulation that works without special processes or skills. The one thing you can do to help bonding is to clean the PCB, which might already be part of your process anyway. I would stay away from No-clean solders for HV (unless you clean them up). But really, you can just assume that creepage can occur along boundaries, smooth or sharp, dirty or clean.

 

[newengr]

The package I'm interested in is TO-263-8. I was trying to look for app notes or anything on this device to determine what voltage I need to start worrying about potting. It's a 3.3 kV device. I may actually see voltages as high as 2.2 kV. What are your thoughts on this one? The pads are back back pad is separated from the pins by 7.2 mm minus any extra for the pads since they will stick over slightly. Id call that 6 mm or maybe less. For 2.2 kV, the clearance/creepage should be at least 11 mm in air according to https://www.smps.us/pcbtracespacing.html.

 

[DaveE]

The package I'm interested in is TO-263-8. I was trying to look for app notes or anything on this device to determine what voltage I need to start worrying about potting. It's a 3.3 kV device. I may actually see voltages as high as 2.2 kV. What are your thoughts on this one? The pads are back back pad is separated from the pins by 7.2 mm minus any extra for the pads since they will stick over slightly. Id call that 6 mm or maybe less. For 2.2 kV, the clearance/creepage should be at least 11 mm in air according to https://www.smps.us/pcbtracespacing.html.

I think you'll be OK. I'm assuming there isn't HV between the small pads. If there is you might cut a small slot between them.

Much of the creepage requirements/guidelines assume bad things along the arc path like humidity, dirt, etc. (hence the pollution degree tables). You won't have those problems. IIRC, from many years ago, the safety standards for fully encapsulated assemblies only require inspection of samples to verify good encapsulation and an appropriate Hi-Pot test on every article. I don't think they include creepage, of they do it will be in the cleanest pollution category.