Shoot-Through on Synchronous Buck Converter

  • #1
PEEng
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1
TL;DR Summary
Antiparallel Schottky diode not preventing "shoot-through on lower MOSFET, even with huge deadtime. What's the cause and how can I reduce it?
Hi, im fairly new to this so this is probably a straight forward question. I'm usimg a half-bridge basically as a synchronous buck converter. I'm not trying to get any specific conversion ratio at the moment, I'm just trying to understand all of the operating principles. One of the things tripping me up right now is a pretty large "shoot-through" that occurrs when I turn on the top MOSFET (Q1). I have a huge deadtime so I know this isn't the issue. I've verified I still have the same issue when I hold the gate of lower MOSFET (Q2) negative basically using it as a freewheeling diode. I've tried slowing down the gate of Q1 and still no change. It takes longer for Q1 to turn on but it's occurring as soon as it passes the miller plateau.

I've added an antiparallel Si schottky with Vf=0.4 @10 A (I'm seeimg just below 10 A). The body diode of the MOSFET is measuring about 0.55 V with the multimeter so I figured the schottky should be the one conducting.

Any suggestions or discussion to help understand what's going in is much appreciated.

**edit**
I'm using a TI evaluation board fully populated by them. The only modifications I made was adding the current sense resistor In line wirh the source of the lower MOSFET. I've attached the datasheet.
 

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  • #2
Circuit layout is one common problem, please attach photo of the hardware along with schematic.

Also photo(s) of dual trace 'scope waveforms if you can manage it, with photos of 'scope ground lead and signal connections so we can see where on the board/circuitry they are connected.

So far you have said the equivalent of "Why won't my car start?", with very little troubleshooting information supplied.

Cheers,
Tom
 
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  • #3
Yes, more data please. Especially scope photos (with good technique). When exactly does the "shoot through" current happen? Is it at turn on (di/dt) of the high side fet, or more in synch with the dV/dt of the switching node (i.e. after the high fet is carrying all of the inductor current). Is it really flowing through the lower FET, or could it be charging the switching node capacitance (inductor, snubbers, Cds, etc.)?

One possible issue is high impedance in the lower gate drive. The dV/dt at the collector can work against that to raise the lower gate voltage enough to conduct. Your test of negative bias there was a really good idea, but you need to verify that that bias can absorb the Cgs current and control the gate at the device when dV/dt is high.

It can be difficult to slow down dV/dt at the switching node, since it's controlled more by the inductor and node capacitance than the high side gate drive. An RC snubber may help; or not, that raises other issues.

Also, how big is it? There is always some extra turn on current in square wave converters. Is this a 100W PS or a 10KW PS? N-MOSFETS? Big ones or tiny? High or low input voltage? Which control IC are you using? Are you worried you are "only" getting 89% efficiency when you think you should have 93%? etc. There is a good reason there are about 1 million app notes and such about SMPS.

Finally, you seem to be asking all of the right questions, which leads me to my generic troubleshooting advice: Go through everything carefully and make sure things are actually the same as your assumptions. Often the difficult problems are the ones we either don't know about or that we misunderstand. I recall spending most of a work day confused with my frequency response data because I forgot to turn on the power supplies to the circuit.
 
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  • #4
Tom.G said:
Circuit layout is one common problem, please attach photo of the hardware along with schematic.

Also photo(s) of dual trace 'scope waveforms if you can manage it, with photos of 'scope ground lead and signal connections so we can see where on the board/circuitry they are connected.

So far you have said the equivalent of "Why won't my car start?", with very little troubleshooting information supplied.

Cheers,
Tom
I'm using an evaluation board made by TI. I don't think they did a good job laying it out as it looks like they gate driver IC is a lot further from the devices than they need to be. I'm guessing that's for ease of testing and making modifications like I'm trying to do. The link to the datasheet is below. I'll also add more info in response to Dave's comments below.

To add a few more details here though, I mentioned I tried this with a schottky diode across the lower MOSFET. I also added a sense resistor In series with the lower MOSFET source. Measurimg the differential voltage using an optically isolated probe. I hope this helps as I'm not able to post waveforms. I understand if you're not able to. I've been beating my head against the wall on this for a few days now and just wanted to see what some other ideas may be.

One other thing which I'll also mention below. The inductor current is 2 A with 0.5 A ripple. The shoot through is from drain to source through the bottom FET with a peak of about 10 A.
 
  • #5
DaveE said:
Yes, more data please. Especially scope photos (with good technique). When exactly does the "shoot through" current happen? Is it at turn on (di/dt) of the high si
DaveE said:
Yes, more data please. Especially scope photos (with good technique). When exactly does the "shoot through" current happen? Is it at turn on (di/dt) of the high side fet, or more in synch with the dV/dt of the switching node (i.e. after the high fet is carrying all of the inductor current). Is it really flowing through the lower FET, or could it be charging the switching node capacitance (inductor, snubbers, Cds, etc.)?

One possible issue is high impedance in the lower gate drive. The dV/dt at the collector can work against that to raise the lower gate voltage enough to conduct. Your test of negative bias there was a really good idea, but you need to verify that that bias can absorb the Cgs current and control the gate at the device when dV/dt is high.

It can be difficult to slow down dV/dt at the switching node, since it's controlled more by the inductor and node capacitance than the high side gate drive. An RC snubber may help; or not, that raises other issues.

Also, how big is it? There is always some extra turn on current in square wave converters. Is this a 100W PS or a 10KW PS? N-MOSFETS? Big ones or tiny? High or low input voltage? Which control IC are you using? Are you worried you are "only" getting 89% efficiency when you think you should have 93%? etc. There is a good reason there are about 1 million app notes and such about SMPS.

Finally, you seem to be asking all of the right questions, which leads me to my generic troubleshooting advice: Go through everything carefully and make sure things are actually the same as your assumptions. Often the difficult problems are the ones we either don't know about or that we misunderstand. I recall spending most of a work day confused with my frequency response data because I forgot to turn on the power supplies to the circuit.

de fet, or more in synch with the dV/dt of the switching node (i.e. after the high fet is carrying all of the inductor current). Is it really flowing through the lower FET, or could it be charging the switching node capacitance (inductor, snubbers, Cds, etc.)?

One possible issue is high impedance in the lower gate drive. The dV/dt at the collector can work against that to raise the lower gate voltage enough to conduct. Your test of negative bias there was a really good idea, but you need to verify that that bias can absorb the Cgs current and control the gate at the device when dV/dt is high.

Also, how big is it? There is always some extra turn on current in square wave converters.

DaveE said:
When exactly does the "shoot through" current happen? Is it at turn on (di/dt) of the high side fet, or more in synch with the dV/dt of the switching node (i.e. after the high fet is carrying all of the inductor current). Is it really flowing through the lower FET, or could it be charging the switching node capacitance (inductor, snubbers, Cds, etc.)?

Your test of negative bias there was a really good idea, but you need to verify that that bias can absorb the Cgs current and control the gate at the device when dV/dt is high.

Also, how big is it? There is always some extra turn on current in square wave converters.
Dave,

Thanks for your reply. Unfortunately I cannot post scope photos but hopefully I can explain. As I mention in the response to Tom, I've been pulling my hair out just trying to figure out what's happening for a few days now. I'm using a TI Evaluation board so I'll post the datasheet and URL to digikey.

The shoot through is happening when the top FET turns on. I lifted the source of the bottom FET and added a sense resistor. I'm measuring the voltage using an optically isolated differential probe so I am positive this is current going through the source. The inductor is 2 A with about 0.5 A ripple. The shoot through is about 10 A.

When the Vgs is applied, I can see the miller plateau. Once Vgs starts to increase again, this is when I see the shoot through. This same pattern happens regardless of the switching speed. I can remove the gate resistor, plus the default 5.1 ohm, or put a 40 ohm and this still holds true. The larger gate resistor takes longer to charge Ciss but once the plateau is passed I get shoot through right away. I verified the negative voltage is holding the lower gate below 0 V by using an isolated probe to measure it. I should also mention for this test I removed Rgbot from the board so it was disconnected from the driver. The negative voltage was referenced to the source side of the current sense resistor. I did this because it was bouncing up and I thought the shoot through may be happening because the gate voltage was jumping and turning the switch in.

After my last statement, I'm positive the switch is off so that leads me to believe current must be flowing through Cdg-Cgs and/or Cds. That's assuming the schottky is working properly which I believe it is because I measured the forward voltage with no current and it was about 0.15 V with it installed but 0.55 V without it.

So to summarize, the magnitude and width of the shoot through does not change regardless of Vgs on the power MOSFET (0 v of -2 V), Rgtop (0 Ohm. 5.1 Ohm, or 40 Ohm). Current is measured using a sense resistor In the lower MOSFET source with an optically isolated probe. Vgs for the top and bottom FETs are also measured using an optically isolated probe.
 

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  • #6
Since you have a schottky freewheeling diode in place, what happens if you disconnect the lower fet drain?

Anyway, it seems like something isn't right here. TI eval boards may not be perfect, but they shouldn't be this bad. Did you use their specified parts?

Have you verified that you don't have instrumentation problems? For example, is something getting too hot? Is your efficiency lower than expected? Have you measured the current with different methods? What happens if you measure the 10A extra current and then move your probe to the "ground" side to verify a zero measurement without any other changes? Be skeptical first, lab technique is a huge issue with these things; scope probes often lie.
 
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  • #7
That PCB layout looks OK to me. I don't think that's your problem.
 
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  • #8
If I remove the fet and have only the schottky, it looks as I expected. Current is flat and there is no reverse recovery. I tried several different schottkys in parallel with the lower fet thinking it was the diode which it may have been. I finally found this one with a much lower forward voltage which is why I took that off the table for now.

I used all TI parts. The board comes fully populated. The only thing I modified was lifting the source leg of the lower fet to add the current sense resistor.

I've measured the current using at least 4 different probes and 2 different scopes. I have slightly different transient response which I attribute to a difference in coupling/tip capacitance the current starts to peak at the same time and the amplitude is about the same. The optical probe which I'm using gives the lowest measurement which I believe is the most accurate.

I really do apologize I can't add photos as I'm sure that would help. One other thing to mention is the current spike coincides with the node voltage rising. As soon as the switch node voltage starts to rise, current starts to shoot through. I've also noticed the ringing on the node voltage is the same frequence as ringing on the source current once it falls. All of this is happening in about 30 ns.

I did not try measuring ground to verify 0 V with no other changes. I'll try that next. I believe ground does shift once the current is already flowing. That's because I measured Vgs on the lower fet using the isolated probe and it reads 0 V. At the same time, I used a passive probe to measure the gate to ground voltage and there's a bounce once the current is already flowing. Remember, I added the sense resistor so the source isn't truly ground. It's only a few mV off but still that's why I measured this. My thought was made ground was bouncing and pushing thr gate above the threshold voltage. This is not the case as I verified it still happens with negative Vgs which does stay negative.
 
  • #9
Since you don't see it with just the schottky, it can't be current flowing to other node capacitance (like the bootstrap caps), plus you wouldn't see that current in the lower source pin anyway. So I still think it's a problem with the Miller effect. Although your negative bias experiment should have fixed that. Of course it has to stay below Vgsth during the switching.

I might try again with the parallel schottky and everything else installed. Then lift the lower gate pin and directly short it to the source. Then you'll know that fet can't turn on, so no miller effect. If you still see it it must be the body diode recovery, plus a little bit of Coss.

What are your fet part numbers? You may need one with lower Qrr or just smaller. Is the amount of the current pulse comparable to the Qrr spec? This is a case where bigger isn't always better.
 
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  • #10
The part is CSD19536KTT. I lifted the lower gate pin and shorted it to the source as recommended. There's no difference in the current spike. It changed with Vds and not Ids which is another thing leading me to believe it was a capacitance issue and not reverse recovery.

The datasheet provides Qrr=548 nC with trr=103 ns, IF= 100 A, Vds=50 V. At about 10 A the pulse width of the current is about 20 ns so much lower Qrr but also much lower current. Either way, the full pulse width is a out 20 ns which is much shorter than thr listed trr=103 ns. Also, not that it makes a huge difference but its probably closer to 18 ns and thats from about 0% back down to 0%. I mention that because trr is measured differently meaning my time would be even less than 18 ns of measured the same way.

Ciss=9.25 nF typical (12 nF max) and Coss=1.82 nF typical (2.37 nF max).

Crss(Cgd)=47 pF. Since I shorted gate-source that shorted Cgs, right? To me, that says if it was Ciss it should've reduced the current magnitude significantly since Ciss=Cgd+Cgs and it looks like Cgs=8.78 nC or an order of magnitude more than Cgd. I'll try to find a fet with much better Coss since it looks like this would be the dominant factor based on all of that listed before. If there are holes I'm this logic or other things to consider, im really interested in hearing them.
 
  • #11
PEEng said:
The part is CSD19536KTT. I lifted the lower gate pin and shorted it to the source as recommended. There's no difference in the current spike. It changed with Vds and not Ids which is another thing leading me to believe it was a capacitance issue and not reverse recovery.
OK, not the Miller effect. Not the gate drive.

PEEng said:
Since I shorted gate-source that shorted Cgs, right?
yes.

So a 10A x 10nsec (square) pulse is 100nC, which when put in a 2nF capacitor will make ΔV=50V.

You have an inductor that is rated for 2A, but a MOSFET rated for 200Aave? Your transistor is way too big, I think. If you had a 100A output, a 10A turn on pulse wouldn't be much of a concern.

Also, be careful with Coss specs. They are really inherited from the realm of linear (RF) operation at a fixed operating point. The capacitances in a SMPS MOSFET are very non-linear with voltage, as you can see in figure 5 on the data sheet.

Finally, not a complaint, but maybe a lesson in communication with other engineers, if you had told us a summary of your design requirements, given us a schematic and a PL, it would have saved us all a bunch of time.

I still don't know what you actually need this circuit to do, but my advice is to steal a design from the application engineers at your favorite big semiconductor company. Their stuff already works, at least for what they intended. The people that pay you really have a problem with development cost and time to market. They probably don't want to pay you to reinvent the wheel. My rule working on satellite PSs and laser electronics (low volume mfg) was simple. If you can buy it from a good source, buy it. If you can get other (application) engineers to do the design for you, copy that stuff. If you have to do it yourself, talk to the engineers that make your key components to learn from their experience. Then spend your time evaluating and testing to make sure the stuff you copied works well for your application. The difficult designs I did were all based on "no one's done exactly this before, but it's kind of like these other things".

There's an old grad school joke: Several weeks spent in the lab can save you from spending a few hours in the library.
 
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  • #12
"A month in the laboratory can often save an hour in the library." — Frank Westheimer.
 
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  • #13
DaveE said:
You have an inductor that is rated for 2A, but a MOSFET rated for 200Aave? Your transistor is way too big, I think. If you had a 100A output, a 10A turn on pulse wouldn't be much of a concern.

That's a good point. I started at lower current just trying to understand all of the details like this, but I plan on increasing the current closer to 80 A. I didn't want to start put also having to worry about thermal.

DaveE said:
Finally, not a complaint, but maybe a lesson in communication with other engineers, if you had told us a summary of your design requirements, given us a schematic and a PL, it would have saved us all a bunch of time.

I still don't know what you actually need this circuit to do, but my advice is to steal a design from the application engineers at your favorite big semiconductor company.
This isn't for a product. I'm just working with this as a learning experience actually.


DaveE said:
My rule working on satellite PSs and laser electronics (low volume mfg) was simple.
Fortunately this is an internship at a smaller company and I'm able to learn as i go. I'm doing this on my own time just because I want to learn things like this. As a side note, sattelite PSs sound challenging for reasons I can can think of and probably even more that I can't. Ive always liked space so would like to go into that area eventually. Im in/from Southern California so theres a lot of that in the area.

Im just starting my Masters. I have the option to take a course at another ABET acreddited university and transfer it in. Are there any courses you can recommend in this area? I'm even open to doing it on my own for professional development. Sorry if this isn't the appropriate place to ask that. I can post it in another thread if so.
 
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  • #14
PEEng said:
sattelite PSs sound challenging for reasons I can can think of and probably even more that I can't.
Challenging, I guess so. But maybe not as interesting as you might think. Extreme reliability requirements means that you use a lot of older technologies and do tons of paperwork analyzing and testing. Some requirements are unusual and not applicable anywhere else.

OTOH, what you do learn is how to do everything carefully the right way. Lots of people looking over your shoulder when you work with the hardware; no cowboy @#$% allowed. For example, I was never allowed to solder the real thing, that required a few pages of paperwork, a QA inspector, and a NASA certified assembler. On one S level project if you reheated a PCB pad 4 times the entire board is thrown away, so you think really hard before you try things. If you replace a part and it isn't fixed, you'll have committee meetings to deal with before anything else happens to that HW. I dislike working in clean rooms and troubleshooting with gloves on. Everything takes a long time. You can get tired of that stuff really fast.

Also, you'll probably never see the satellite or understand what it does. For DOD stuff you probably won't even know if they ever used your stuff or if it worked. You will have requirements to meet that you don't understand, and they won't explain. Lots of BS (and some real) security stuff to deal with, chief among that is "need to know"; you'll probably never have much of that. That means that you can't talk to the engineers that your stuff interfaces with, that's all done in documents prepared by people that work in secure facilities and don't understand what either of you are trying to figure out.

I'm glad I did it for a while, I learned a lot. I'm also really glad I left before I got trapped with the golden handcuffs. My next commercial job was better in every way.

PEEng said:
Im just starting my Masters. I have the option to take a course at another ABET acreddited university and transfer it in. Are there any courses you can recommend in this area?
Sorry, I don't know what you already know, or what you want to learn. I'm also a few decades removed from the academic world; I don't know what's available to you.
 

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