ADC/DAC Sample Rate and Reference Voltage

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Discussion Overview

The discussion focuses on the functionality and implications of the reference voltage (Vref) in an ADC (Analog-to-Digital Converter) circuit, particularly in relation to sample rates and maximum encoded values. Participants explore the relationship between Vref, sample rates, and the ADC's specifications, specifically referencing the Microchip MCP3004.

Discussion Character

  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant asserts that the Vref pin on an ADC chip sets the maximum encoded value for voltage, suggesting that tying a lower voltage to Vref scales the output accordingly.
  • Another participant agrees with the initial assertion about Vref but questions why the sample rate would depend on Vref, proposing that it might actually depend on Vdd instead.
  • A participant expresses confusion about the relationship between sample rate and Vref, indicating that it seems more logical for sample rate to depend on Vdd.
  • One participant references the datasheet of the MCP3004, noting that it lists maximum sampling rates at different Vdd values, which aligns with their assumption that Vdd influences sample rate rather than Vref.
  • A later reply acknowledges a misunderstanding regarding the bit resolution of the ADC, initially questioning if an 8-bit ADC would be faster than a 10-bit ADC under the same conditions, but then retracts this statement upon realizing the throughput is determined by Vdd.

Areas of Agreement / Disagreement

Participants generally agree that Vref sets the maximum value for voltage encoding, but there is disagreement and uncertainty regarding the influence of Vref versus Vdd on the sample rate. The discussion remains unresolved regarding the specific dependence of sample rate on these parameters.

Contextual Notes

Participants reference the datasheet for the MCP3004, indicating that the relationship between Vref, Vdd, and sample rate may depend on specific conditions outlined in the documentation. There is also a noted confusion about the implications of bit resolution on throughput.

tomizzo
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I am currently working on a circuit design that is featuring both a ADC and DAC. I'll focus my question on the ADC in this thread.

I'm trying to figure out what each pin does. Am I correct in assuming that the Vref pin on the an ADC chip is used as the maximum encoded value for a voltage? Say for example I have an ADC capable of encoding a 0-5V signal with 8 bits of resolution. And then say that I only want to be measuring a maximum voltage of 2V. If I were to tie 2V to the Vref pin, this should scale the encoded values 0-255 to correspond with voltages from 0-2V. Correct?

However, I noticed on a recent data sheet that the sample rate of the ADC is dependent on the value of Vref (see image below). Why is this? Why would the sample rate depend on what is set to the Vref pin?

Any help regarding this?
 

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The reference voltage is the maximum value for the conversion as you correctly thought. The rate then would be determined by the size of each chunk of from the 8 bit value. i.e. Vref/256
 
dlgoff said:
The reference voltage is the maximum value for the conversion as you correctly thought. The rate then would be determined by the size of each chunk of from the 8 bit value. i.e. Vref/256
Could you expand on why the sample rate is dependent on the value of Vref? Or is the data sheet saying that the sample rate is actually dependent on the value of Vdd which just happened to be the same as Vref?
 
That's weird. It's not obvious why the sample rate would depend on Vref. I could see it depending a bit on Vdd, but not Vref.

Which chip is it?
 
berkeman said:
That's weird. It's not obvious why the sample rate would depend on Vref. I could see it depending a bit on Vdd, but not Vref.

Which chip is it?

It is a Microchip MCP3004 (data sheet: http://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf).

The more I look at this, the more I'm starting to assume that the sample rate is dependent on the value of Vdd and not Vref. They simply were listing an example in which case Vdd would be 5.0V or 2.7V in which case the maximum Vref would also have to be 5.0V and 2.7V respectively.
 
Yeah, that would make more sense. And that's how it's listed in the opening bullets of the datasheet:

• 200 ksps max. sampling rate at VDD=5V
• 75 ksps max. sampling rate at VDD=2.7V

:-)
 
But it's a 10 bit ADC. Wouldn't it be faster with 8 bits as opposed to 10 bits? Assuming the same clock rate.

Edit: Okay. Disregard this. I see my mistake. It is VDD that "determines" throughput.
 
Last edited:

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