Are WAW and WAR hazards unique to RISC processors?

[user366312]

TL;DR Summary

Whenever I find something on hazard, I find it in the context of RISC processors like MIPS.

Are WAW and WAR hazards unique to RISC processors?

Or, CISCs can also encounter those hazards?

 

[willem2]

You get this hazards with any pipeline architecture that can modify data in more than one stage.

 

[Klystron]

Summary: Whenever I find something on hazard, I find it in the context of RISC processors like MIPS.

Are WAW and WAR hazards unique to RISC processors?

Or, CISCs can also encounter those hazards?

In my experience a data hazard can be encountered on CISC as well as RISC processors.

 

[.Scott]

CPU hazards are the result of pipeline processing - either CISC or RISC. If there is no pipe-lining, you might still run into WAW, WAR, and RAW issues, but they would be handled in the software as resource arbitration issues.