Can we use 74LS73 ICs for master-slave JK flip flop?

[challarao]

Hi everybody...
This is not actually a home work question...i didn't find any other place to post it...
1.Can we make master slave jk flipflop using 74LS73 ic's which containt two individual jk flipflops?



2.JK flip flop has two 3-input NAND gates and the outputs are fed back from its own outputs Q and Q'.


3. I know that jk flipflop itself has feed back connection from its previous output to its 3 input NAND gates along with the clock input and j-k inputs.But,master slave need to be fed back from its slave's previous output, not from its own output...when 74LS73 contain two jk flipflops with outputs fed back to NAND gates... i think it's not possible use this ic for master slave flipflop...I did many searches on this but found no answer...please help me...

References: IC's internal structure can be found at...
www.electronics-tutorials.ws/sequential/seq_2.html
Image: http://www.google.co.in/gwt/x/i?source=wax&u=http%3A%2F%2Fwww.electronics-tutorials.ws/sequential/seq17.gif&wsi=48dfd7a664f38923&ei=yIKaT8KoG6nbmAWF5bXyBQ&wsc=tf

 

[NascentOxygen]

1.Can we make master slave jk flipflop using 74LS73 ic's which containt two individual jk flipflops?

http://img69.imageshack.us/img69/2577/iconthumb.gif The tutorial you linked to states exactly that.

3. I know that jk flipflop itself has feed back connection from its previous output to its 3 input NAND gates along with the clock input and j-k inputs.But,master slave need to be fed back from its slave's previous output, not from its own output...when 74LS73 contain two jk flipflops with outputs fed back to NAND gates...

QUOTE: The 74LS73 is a Dual JK flip-flop IC, which contains two individual JK type bistable's within a single chip enabling two JK flip-flops[/color] or one [/color]master-slave toggle flip-flop to be made.[/color]

i think it's not possible use this ic for master slave flipflop...I did many searches on this but found no answer...please help me...

Versatility is the whole reason for manufacturing the chip that way. ::EDIT:: I just noticed what has you worried—the extra feedback in the slave. I think you will find that the feedback is of identical state with those gates other inputs such that it has nil effect. If you feed a HIGH to a spare input of any AND or NAND gate, you cause no change in its operation. In the same vein, if you feed a LOW to a spare input of a AND or NAND gate you are simply duplicating the effect of a LOW that already exists on one of that gate's other inputs. Feeding Q and ¬Q from the master to the J and K inputs of the slave is unaffected by also feeding the slave's Q and ¬Q to its own J and K inputs provided the slave's Q and ¬Q simply duplicate the effect of the Q and ¬Q from the master. (They don't have to be identical to have no effect on operation.)

References: IC's internal structure can be found at...
www.electronics-tutorials.ws/sequential/seq_2.html
Image: http://www.google.co.in/gwt/x/i?source=wax&u=http%3A%2F%2Fwww.electronics-tutorials.ws/sequential/seq17.gif&wsi=48dfd7a664f38923&ei=yIKaT8KoG6nbmAWF5bXyBQ&wsc=tf

Including references was very useful. I would not have gone looking for them, so would not have answered this had you not provided that assistance.

 

[NascentOxygen]

Adding some more to my post...

To construct a MASTER-SLAVE using the 74LS73 it appears you will need to add a pair of external NAND gates—you'll need to form J NAND ¬Q_slave to feed to pin 14 of the MASTER, and the same idea goes for pin 3. The feedback of the MASTER's output to its own input is, as I explained above, probably inconsequential.

There is a chance it may be feasible to do something dodgy that avoids the need to use external gates, but you are probably not interested in exploitative shortcuts. [/size]

 

[challarao]

Thank you very much...
that helped me a lot...
"Does my post come under home work question?"

There is a chance it may be feasible to do something dodgy that avoids the need to use external gates, but you are probably not interested in exploitative shortcuts. [/size]

Yeah, but I want to know every alternative...
Thank you...

 

[challarao]

http://img69.imageshack.us/img69/2577/iconthumb.gif

Versatility is the whole reason for manufacturing the chip that way. ::EDIT:: I just noticed what has you worried—the extra feedback in the slave. I think you will find that the feedback is of identical state with those gates other inputs such that it has nil effect. If you feed a HIGH to a spare input of any AND or NAND gate, you cause no change in its operation. In the same vein, if you feed a LOW to a spare input of a AND or NAND gate you are simply duplicating the effect of a LOW that already exists on one of that gate's other inputs. Feeding Q and ¬Q from the master to the J and K inputs of the slave is unaffected by also feeding the slave's Q and ¬Q to its own J and K inputs provided the slave's Q and ¬Q simply duplicate the effect of the Q and ¬Q from the master. (They don't have to be identical to have no effect on operation.)

Including references was very useful. I would not have gone looking for them, so would not have answered this had you not provided that assistance.

I got a doubt...Master Slave Flip flops are introduced in order to avoid the racing condition...Since, slave can't be working when master's clock is high there would be no racing in original Master Slave's circuit...But, can the method described by you avoid racing of flip-flops...I got this doubt because the flip-flop outputs are connected to their own inputs...

 

[Antiphon]

It can't be done with the 7473 for the reason described by Challarao.

You use the 7472 if you need a MS JK flip flop.

 

[NascentOxygen]

The Fairchild application notes describe its use as MASTER-SLAVE JK
http://www.datasheetarchive.com/74LS73 dual JK-datasheet.html#contextual

"J and K inputs must be stable one setup time (~20ns) prior to the HIGH-LOW clock transition for predictable operation." This may or may not be important in some apps.

 

[Antiphon]

The Fairchild application notes describe its use as MASTER-SLAVE JK
http://www.datasheetarchive.com/74LS73 dual JK-datasheet.html#contextual

"J and K inputs must be stable one setup time (~20ns) prior to the HIGH-LOW clock transition for predictable operation." This may or may not be important in some apps.

You misread the Fairchild data sheet. The master-slave JK is the 9020 and the 9022. The 7473 is two separate JK, not a master slave arrangement.