JK flip flop master slave - Master remembers?

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SUMMARY

The discussion centers on the behavior of the JK master-slave flip-flop, particularly how the master "remembers" changes to the J and K inputs during the clock's high phase. The key takeaway is that while the clock is high, any changes to J and K are stored in the master, but only the final state is transferred to the slave when the clock goes low. The internal circuit design, where the slave's output influences the master's input, is crucial for understanding this memory behavior. This mechanism is often referred to as the "one's catcher," which highlights the flip-flop's ability to retain the last significant input state.

PREREQUISITES
  • Understanding of JK flip-flop operation
  • Familiarity with clock pulse behavior in digital circuits
  • Knowledge of master-slave flip-flop configurations
  • Basic digital logic design principles
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  • Study the internal circuit design of JK master-slave flip-flops
  • Learn about the implications of gated SR latches in flip-flop designs
  • Explore timing diagrams for JK flip-flops to visualize state changes
  • Investigate other types of flip-flops and their memory characteristics
USEFUL FOR

Electronics students, digital circuit designers, and anyone studying sequential logic circuits will benefit from this discussion on JK flip-flops and their unique memory behavior.

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NB: Got a bit wordy, highlighted question in red.

Homework Statement


Just a picture of what we're dealing with.

I'm given a clock pulse, J and K inputs, and asked to describe the JK master-slave flip flop output.

Homework Equations



J K Q(t+1)
0 0 Q(t) No change
0 1 0 reset
1 0 1 set
1 1 Q'(t) Complement

The Attempt at a Solution



I understand:

Clock = 1 -> Master value can be modified by changes to J and/or K
Clock = 0 -> Value of Slave is set to that of Master

4TavN.jpg


Sorry for the drawing, I hope it is sufficient. During the positive clock phase I called 2, there is a brief blip in the J.

J & K are both 1, so I complement the Master value. it is now 1.

Now here is where I get uncertain. As I understand it, ANY change in J and/or K, even if there are 1000 changes, during a positive clock phase, will be reflected in the master. So only the FINAL value, once the clock drops from 1 to 0, in the master, "sticks".

So I say: that blip in J, well it drops quickly, during a positive clock phase, and so that leaves us with J = 0, K = 1, which is reset, so I drop the Master to 0 again.

However, this professor:



(skip to 4:10)

he's got an image from a book that says: "...something tricky about the master-slave, it's called the "one's catcher", it remembers any activity on the J or K while the clock is high. The J went high, then it went low, but it remembers".

It remembers? Can somebody explain how it remembers?
 
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You have to take a look at the internal circuit, video at 1:30.

The SR for the master is *gated* by the constant output from the slave. If the slave has Q=1, setting J=1 on the master is ignored. Likewise if the slave has Q=0, setting K=1 on the master is ignored. In other words, if slave Q=1 you can only reset the master bit and if slave Q=0 you can only set the master bit with no way to take it back.

I suppose this turns into 'remembering ones', which may be a good mnemonic device once it's confirmed, but it doesn't teach anything :-/
 
Oh yeah. I see the Q and Q' values from the slave are wired back into the input gates of the master. That has some implications I have to take into account.

I agree with your statement on remembering ones. I can't accept that without understanding it, so thanks a lot for your help! Gonna take another look at this task tomorrow and make some adjustments. ;)
 

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