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JK flip flop master slave - Master remembers?

  1. Nov 5, 2012 #1
    NB: Got a bit wordy, highlighted question in red.

    1. The problem statement, all variables and given/known data
    Just a picture of what we're dealing with.

    I'm given a clock pulse, J and K inputs, and asked to describe the JK master-slave flip flop output.


    2. Relevant equations

    J K Q(t+1)
    0 0 Q(t) No change
    0 1 0 reset
    1 0 1 set
    1 1 Q'(t) Complement



    3. The attempt at a solution

    I understand:

    Clock = 1 -> Master value can be modified by changes to J and/or K
    Clock = 0 -> Value of Slave is set to that of Master

    4TavN.jpg

    Sorry for the drawing, I hope it is sufficient. During the positive clock phase I called 2, there is a brief blip in the J.

    J & K are both 1, so I complement the Master value. it is now 1.

    Now here is where I get uncertain. As I understand it, ANY change in J and/or K, even if there are 1000 changes, during a positive clock phase, will be reflected in the master. So only the FINAL value, once the clock drops from 1 to 0, in the master, "sticks".

    So I say: that blip in J, well it drops quickly, during a positive clock phase, and so that leaves us with J = 0, K = 1, which is reset, so I drop the Master to 0 again.

    However, this professor:



    (skip to 4:10)

    he's got an image from a book that says: "...something tricky about the master-slave, it's called the "one's catcher", it remembers any activity on the J or K while the clock is high. The J went high, then it went low, but it remembers".

    It remembers? Can somebody explain how it remembers?
     
    Last edited by a moderator: Apr 19, 2017
  2. jcsd
  3. Nov 5, 2012 #2
    You have to take a look at the internal circuit, video at 1:30.

    The SR for the master is *gated* by the constant output from the slave. If the slave has Q=1, setting J=1 on the master is ignored. Likewise if the slave has Q=0, setting K=1 on the master is ignored. In other words, if slave Q=1 you can only reset the master bit and if slave Q=0 you can only set the master bit with no way to take it back.

    I suppose this turns into 'remembering ones', which may be a good mnemonic device once it's confirmed, but it doesn't teach anything :-/
     
  4. Nov 5, 2012 #3
    Oh yeah. I see the Q and Q' values from the slave are wired back into the input gates of the master. That has some implications I have to take into account.

    I agree with your statement on remembering ones. I can't accept that without understanding it, so thanks a lot for your help! Gonna take another look at this task tomorrow and make some adjustments. ;)
     
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