Comparator design using a 4-bit adder

AI Thread Summary
The discussion focuses on designing a 4-bit magnitude comparator using a single 4-bit adder and various logic gates for signed numbers in two's complement format. The original poster is unfamiliar with comparator design and seeks guidance on creating a truth table and understanding the role of carry inputs. Participants emphasize the importance of using two's complement and suggest constructing a truth table to analyze the 16 possible combinations of inputs. There is clarification needed regarding the absence of carry inputs in the design and the proper implementation of the logic gates. Overall, the conversation highlights the challenges of the task and the necessity for a structured approach to comparator design.
ichabodgrant
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Homework Statement


Hi, it's me again.
Now I am going to design a 4-bit magnitude comparator using just ONE 4-bit adder and infinitely large number of gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) for signed numbers (negative binary).

a 4-bit magnitude comparator using 4-bit adder for signed values.png


Homework Equations


A > B => A3barB3 + A2barB2x3 + A1barB1x3x2 + A0barB0x3x2x1

similar for A < B and A = B.

The Attempt at a Solution


a 4-bit magnitude comparator using 4-bit adder for signed values_attempts.png
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This is my attempt. Frankly, this is my first time encountering problems related to comparator design because this is never said to be in the syllabus of the course (introductory course). I find this in a past paper... seemingly indicating that the instructor wants us to divide and conquer it within the 3 hours of exam.

I do this all by resources on the internet. So there may be a lot of mistakes.
 
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I think you are on the right track, but I have some comments:
  • Where is the Cin coming from? You are only comparing two 4-bit numbers!
  • Are the numbers supposed to be in two's complement?
And - there are only 16 combinations possible. I suggest making a truth table before continuing.
 
I think it should be using 2's complement.
 
ichabodgrant said:
I think it should be using 2's complement.
Then get busy on your truth table.
 
A truth table looks like this? because I have never drawn a truth table for such a design...so I searched on google...
 

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I have a question about the XOR gates. Are those XOR gates for doing 2's complement (i am thinking in this way)?
But I know that 2's complement is not just inverting 1 and 0, but also needs to add 1 after that. It seems that the above design cannot do that?
 
And you mentioned that there should not be Cin? Does this mean there are no cascading inputs?
 
ichabodgrant said:
A truth table looks like this? because I have never drawn a truth table for such a design...so I searched on google...
No. I meant the truth table for what you are trying to design. Since you are trying to compare two 4-bit 2's complement numbers, create a table with the A-numbers horizontally (-8 to +7) and the B-numbers vertically (-8 to +7). Now fill in the interior of the table with the result of the comparison you want (e. g. A>B). After you have done that, start thinking about how to implement it.
 
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