How Can You Solve Boolean Expressions Using Only NAND and NOR Gates?

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SUMMARY

This discussion focuses on solving Boolean expressions using only NAND and NOR gates, specifically addressing homework questions involving logical representations and circuit design. The participants provided attempts at solutions for two expressions: Q1a) A.B + ~(A.C).~(B+C) and Q1b) (A XOR B) + ~(A XOR B).(B + C). Additionally, the discussion includes designing a combinational logic circuit for converting a 4-bit sign magnitude representation to a 4-bit 2's complement representation and creating a 2-bit adder circuit using multiplexors. Key resources and tips for further understanding were shared, emphasizing the importance of mastering NAND and NOR gate applications.

PREREQUISITES
  • Understanding of Boolean algebra and logic gates
  • Familiarity with NAND and NOR gate functionalities
  • Knowledge of combinational logic circuit design
  • Basic concepts of binary number representations, including sign magnitude and 2's complement
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  • Study the implementation of Boolean expressions using only NAND gates
  • Learn about designing combinational circuits for number representation conversions
  • Research the design and function of multiplexors in digital circuits
  • Explore resources on adder circuit designs, particularly using multiplexors
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Students and professionals in electrical engineering, computer science, and digital logic design who are working on Boolean algebra, circuit design, and digital systems optimization.

Berbanog
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Edited Q1 + solution attempts

Homework Statement



Q1: Represent the following using only NAND gates, and only NOR gates
Q1a) A.B + ~(A.C).~(B+C)
Q1b) (A XOR B) + ~(A XOR B).(B + C)

Q2: Design a combinational logic circuit that converts a 4 bit sign magnitude representation of a number to a 4 bit 2-s complement representation.

Q3: Suppose you require a 2 bit adder circuit. That is, a binary number xy is to be added to a binary number uv in order to yield a binary number abc. Design such an adder circuit using three 16:1 multiplexors. Show how the circuit can also be designed using three 8:1 multiplexors.

Homework Equations


Far as I'm concerned there aren't much 'equations' to write...

The Attempt at a Solution


Q1a) This was answer i got = ~(~A+~B~(~A+~C)+~(~B.~C))
To solve it, i worked backward and started with NAND/NOR gate over the entire equation and found the variable that fits in it that is equal to the original equation.
Q1b) ~(A XOR B) = ~A XOR B <-- i believe i needed to use this to solve this question, but don't think i was getting any closer to getting the solution to this...
Q2 + Q3: I have no clue what these questions are trying to ask...! If someone could give any tips/sites that may help, i will appreciate it very much :D

no need to hurry since I'm still solving them myself, but questions difficult to solve always generate headaches!
 
Last edited:
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Berbanog said:

Homework Statement



i put brackets to represent the bar on top of variables
(A.C) = (A.C)
[A.C] = A'+C'
and XOR sign been replaced with '(X)'

Q1: Represent the following using only NAND gates, and only NOR gates
Q1a) A.B + [A.C].[B+C]
Q1b) A (X) B + [A (X) B](B + C)

Q2: Design a combinational logic circuit that converts a 4 bit sign magnitude representation of a number to a 4 bit 2-s complement representation.

Q3: Suppose you require a 2 bit adder circuit. That is, a binary number xy is to be added to a binary number uv in order to yield a binary number abc. Design such an adder circuit using three 16:1 multiplexors. Show how the circuit can also be designed using three 8:1 multiplexors.

Homework Equations


Far as I'm concerned there aren't much 'equations' to write...

The Attempt at a Solution


Q1a) This was answer i got = [A'+B'[A'+C']+[B'C']]
To solve it, i worked backward and started with NAND/NOR gate over the entire equation and found the variable that fits in it that is equal to the original equation.
Q1b) [A (X) B] = A' (X) B <-- i believe i needed to use this to solve this question, but don't think i was getting any closer to getting the solution to this...
Q2 + Q3: I have no clue what these questions are trying to ask...! If someone could give any tips/sites that may help, i will appreciate it very much :D

no need to hurry since I'm still solving them myself, but questions difficult to solve always generate headaches!

Welcome to PhysicsForums!

Regarding your first question, I have a hard time deciphering what's going on. Here's a tip: you can use inline [iline]\LaTeX[/iline] with the [iline ] tag (switch to advanced composition and click on the little sigma button to bring up the LaTeX reference.) However, standard (VHDL) notation is to represent a NOT using a forward slash (\) or a tilde (~) in front of something, like \A or ~(A&B). An OR is just the plus sign, and an AND is, of course, just an &.

So, maybe I'm misreading but, I believe at one point, you use ~(A & B) (A NAND B) and simplify down to ~A & ~B (NOT A AND'ed with NOT B), but these do not commute this way. If you continue reading in your textbook, you'll find that NAND and NOR can be used to build every other type of gate. You can go in the forwards direction by replacing the unitary / binary operators with NANDs and NORs instead, and trying to simplify:
http://en.wikibooks.org/wiki/Digital_Circuits/NAND_Logic
http://en.wikibooks.org/wiki/Digital_Circuits/NOR_Logic

For Question 2, you'll need to do some additional reading in your textbook on sign formats, and sign conversions. Basically, you want to design a so-called black box that takes an input, in sign + magnitude representation, and then outputs the number in 2's complement. You can start with the Wikipedia article, but you should read through the pertinent textbook sections:
http://en.wikipedia.org/wiki/Signed_number_representations

For Question 3, they want you to use multiplexors (and simple logic gates) to realize mathematical functions. You want your inputs going to the given multiplexers in such a way that the output happens to be the sum of the inputs. To get you started on that topic:
http://www.play-hookey.com/digital/adder.html
http://www.play-hookey.com/digital/multiplexer_two_input.html
http://www.play-hookey.com/digital/decoder_demux_two.html
 
Last edited by a moderator:
*Edit! As 'MATLABdude' wanted i have edited my questions into the correct format

Q1: Represent the following using only NAND gates, and only NOR gates
Q1a) A.B + ~(A.C).~(B+C)
Q1b) (A XOR B) + ~(A XOR B).(B + C)
 

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