CPU Register Components: Buses and 1 Byte

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Discussion Overview

The discussion revolves around the architecture of CPU registers, specifically focusing on the number of buses and their relation to data transfer in an 8-bit CPU context. Participants explore the implications of having 8-bit buses in relation to 32-bit registers and the overall design of CPU components, including the ALU and various registers.

Discussion Character

  • Technical explanation, Conceptual clarification, Debate/contested

Main Points Raised

  • One participant suggests that if there are eight wires connected to the register components, data can travel 8 bits at a time, implying that a 32-bit value would require four transfers.
  • Another participant questions the architecture, noting that they have not encountered a 32-bit register with only 8-bit internal buses and proposes the possibility of a 64-bit CPU where the wires represent a byte.
  • A third participant clarifies that the architecture is an 8-bit CPU with four independent 8-bit registers and describes the role of the accumulator and result registers in relation to the ALU.
  • One participant seeks clarification on missing components, specifically asking about the Instruction Address Register and Memory Address Register, and inquires about learning resources related to the diagram presented.
  • Another participant compares the discussed architecture to the 6502 and mentions that there are both missing and additional components compared to other architectures like the 8085 or Z80.
  • A participant expresses a desire for brief learning resources and asks for book recommendations related to the 8085 architecture.

Areas of Agreement / Disagreement

Participants express differing views on the architecture of the CPU in question, with no consensus reached regarding the specific design or components involved. The discussion remains unresolved regarding the completeness of the architecture and the appropriate learning resources.

Contextual Notes

There are limitations in the discussion regarding assumptions about the CPU architecture, the definitions of registers and buses, and the specific context of the diagram referenced. Participants do not fully clarify the addressing mechanisms or the completeness of the architecture.

nabil__
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In a CPU there are eight wires (buses) connected to the register components.
which means the data can travel 8 bits as a time ? if the register is 32 bit and the value i want to store in a specific register the data must be travel 4 times in a row and store the binary value to a register?
 
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If the wires really represents one bit, then yes.
However, I've never heard of such weird CPU architecture where 32 bit registers had only 8 bit internal buses. Could you please give more details?

Alternative is, that actually it's a 64 bit CPU where the 'wires' would represent a byte. Then to transfer 32 bit would require just one cycle of 'half-bus'.
 
OK it's just a simple 8 bit CPU. Kind of like part of the good old 6502 (with some differences).
There is no 32 bit register: those are four independent 8 bit registers. Let's name them R0 to R3. There is one more 'accumulator' register providing one input for the 8 bit ALU, and also there is one 'result' register for the output of the ALU.

The ALU requires two input byte. One is provided by the accumulator, which you have to load with the data you want to use: one is provided by the register block.
All the addressing and such is missing.

What's now happening on the picture is that according to the 'instruction' the control unit sets the ALU to do something between the content of the accumulator and R0.
The result available from the 'result' register.
 
Rive said:
All the addressing and such is missing.
You mean "Instruction Address Register" & "Memory Address Register" ?
Apart from those what else is missing ? Can i follow this diagram to learn ?
 
Last edited:
Can't tell: compared to a 6502-like architecture there is only a few things missing (also, there are a few extra): compared to a 8085 or Z80, many things are missing or connected the wrong way.
It would be good to know if there was a specific CPU family for the diagram or it's just a sketch.

For 6502 reference you can check here. Apart from the explanation and some sequences there is also a data path there.
 
Rive said:
8085
I want to learn more briefly. Is thee any book you can suggest me which might be good fit for me.
 

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