Decrement with J-K FF and gate/gates

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Discussion Overview

The discussion revolves around constructing a synchronous down counter using J-K flip-flops and gates, focusing on the correct interpretation of the clock input (CP) and the state diagram provided. Participants explore the implications of the circuit design and the clarity of the problem statement.

Discussion Character

  • Homework-related
  • Debate/contested
  • Technical explanation

Main Points Raised

  • One participant expresses uncertainty about the correctness of their initial circuit diagram for the down counter.
  • Another participant points out that the J and K inputs on the least significant bit (LSB) are connected incorrectly and suggests that an input is missing.
  • There is a discussion about the standard way to display flip-flops and gates, with one participant humorously noting the potential negative reaction from an electrical engineering professor to a non-standard layout.
  • Participants share personal experiences regarding the confusion caused by the arrangement of the most significant bit (MSB) and LSB in circuit diagrams.
  • One participant questions the original problem statement, noting that if CP is always high, it is unclear how the flip-flops would change state.
  • Another participant suggests that the state diagram is ambiguous regarding the conditions under which state transitions occur, proposing a clearer notation for indicating state changes.
  • There is a mention that J-K flip-flops typically change state on the falling edge of the clock, raising concerns about the phrasing of the problem statement.
  • One participant acknowledges that the problem may be poorly worded due to translation issues from Swedish to English.

Areas of Agreement / Disagreement

Participants express differing views on the clarity of the problem statement and the implications of the state diagram. There is no consensus on the best way to interpret the clock input and its effect on the counter's operation.

Contextual Notes

The discussion highlights potential ambiguities in the problem statement and the state diagram, as well as the impact of circuit diagram presentation on understanding. There are unresolved questions regarding the timing of state changes in relation to the clock input.

ogward
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It looks like the J and K inputs on the LSB are connected together and connected to one of the AND inputs. But nothing is connected to them as an input. Also the i input is missing. Is that your missing input? I know, I know, the answer is yes, and with that change your circuit is logically fine.

But the standard way of displaying flip-flops and gates is with the inputs on the left and the outputs on the right. Look at your circuit in a mirror and it would be properly displayed.
 
LCKurtz said:
It looks like the J and K inputs on the LSB are connected together and connected to one of the AND inputs. But nothing is connected to them as an input. Also the i input is missing. Is that your missing input? I know, I know, the answer is yes, and with that change your circuit is logically fine.

But the standard way of displaying flip-flops and gates is with the inputs on the left and the outputs on the right. Look at your circuit in a mirror and it would be properly displayed.

what about now?
http://img35.imageshack.us/img35/3654/20111015001.th.jpg
 
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Much better. And correct too.
 
ogward, I got to tell you I almost had a heart attack when I looked at your first circuit diagram. My mind absolutely rebelled and I felt like making the sign of the cross to ward off evil (and I'm not even religious).

THAT'S the kind of response you're likely to get from an EE prof if you draw your circuits right to left. :smile:

(well, OK, I might be a BIT extreme)
 
Hehe you are are probably right i just didn't like the Idea of heaving the MSB on the right side and the LSB on the left, made me a bit confused :P

Thanks for your pointers!
 
ogward said:
i just didn't like the Idea of heaving the MSB on the right side and the LSB on the left, made me a bit confused

I'll be darned. It's been probably 35 years since I've designed those circuits but I DO remember now having exactly the same thought back when I started. You get used to it.
 
ogward said:
Hehe you are are probably right i just didn't like the Idea of heaving the MSB on the right side and the LSB on the left, made me a bit confused :P

Thanks for your pointers!

If you like the LSB flip-flop on the right, just put it there. What's the problem?
 
I thought it wouldn't work that way so I didn't want to experiment with something that works.
But I've tried it and it works, no problems.
 
  • #10
1. Homework Statement [/b]
Construct a synchronous down counter with J-K FFs and gate/gates. It should only count when the CP is high, look at the state diagram.
Is the original problem stated correctly? If CP is being used as the clock input into the JK flip-flops and it is always high, how do the flip-flops change state (count)?
 
  • #11
I formulated it wrong, it should count when the CP goes from 0 to 1 as stated in the state diagram.
 
  • #12
Maybe I am picking nits (to get out of doing housework...), but the state diagram is not clear about CP going from 0 to 1 causing a state transition. If I read the state diagram literally, when CP is 0: stay in same state, when CP is 1: change state. So when CP is 1, the diagram says that the states are constantly changing. Apparently that is not what you want to do, but that is what the diagram is saying (to me, anyway). I would propose adjusting your notation somehow to indicate if CP is either a 0 or a 1: stay in same state, if there is a transition from 0 to 1 (perhaps a rising edge symbol) go ahead and change state.
 
  • #13
Of course JK flip-flops change state at the falling edge of the clock. I wondered about the "only change state when the CP is high" too. That doesn't make sense to me for a clocked state machine using JK flip-flops. The proposed solution runs the counter downward counting on every clock pulse falling edge when i = 1 and pausing when i = 0.

It seems like a correct solution to a poorly worded problem to me. Perhaps the OP will return with his teacher's comments later.
 
  • #14
You guys are right. It is probably poorly worded because I had to translate everything from swedish to english.
And yes I can get back with my professors notes.
 

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