Design ultralow power, narrow band ADC

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Discussion Overview

The discussion revolves around the design of an ultralow power, narrow band Analog-to-Digital Converter (ADC) with specific requirements: a 20MHz input frequency, a bandwidth of 20MHz, an effective number of bits (ENOB) greater than 4, and a power consumption of less than 1mW. Participants explore various architectures and approaches suitable for these specifications.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • One participant suggests that to convert a 20MHz signal, a converter operating at 40Msps is needed, or two converters at 20Msps, noting that the best commercial unit available operates at 50mW for 8 bits.
  • Another participant proposes using a resistive divider with 15 comparators, but highlights that this configuration would consume about 45mW, which exceeds the power requirement.
  • Some participants discuss the possibility of reducing power consumption through signal preprocessing, asking for more details about the signal modulation characteristics.
  • A later reply mentions the potential of a 4-bit ADC design using a flash architecture, which would require only 15 comparators, depending on the fabrication process used.
  • References to existing literature are provided, including a specific paper on a low power asynchronous SAR ADC that could be relevant to the design challenge.
  • One participant questions whether the original poster intends to design an integrated circuit (IC), suggesting that the search for suitable ADCs may not have been thorough enough.
  • Another participant references a discussion on very low power SAR ADCs, indicating that various methods, including switched capacitors, could be explored.

Areas of Agreement / Disagreement

Participants express differing views on the feasibility of achieving the specified power consumption with the desired performance. While some suggest potential architectures, there is no consensus on a definitive solution or approach.

Contextual Notes

Participants note limitations related to the power consumption of proposed architectures and the dependency on specific fabrication processes. There are also unresolved questions regarding the modulation of the input signal, which could influence design choices.

Who May Find This Useful

Individuals interested in low-power electronics design, particularly in the context of ADCs, as well as those exploring innovative approaches to signal processing and circuit design.

anhnha
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Hi,
I want to design an ADC with these specifications:
Fin = 20MHz
BW= 20MHz
ENOB > 4
Power consumption P < 1mW
Could anyone suggest me some ADC for this kind? I have searched a lot in
IEEE but there are only two ADC with SAR ADC and time-interleaved ADC.
The ultralow power consumption makes it hard for me to find a
architecture. I have little experience about this. Kindly help me.
 
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You like a challenge don't you !

To convert a 20MHz signal Nyquist says you will need one converter at 40Msps or two at 20Msps.
The best commercial unit would be 8 bits at about 50mW. But you only want 4 bits.

A resistive divider with 15 comparators might be possible but 15 comparators at 40MHz (= 25ns) will draw about 15ma at 3 volts = 45mW. You might minimise the power slightly by using 15 AC coupled single transistors as your comparators. A sample pulse switches AC inputs from reference to signal at 40Msps.

Maybe some knowledge of your signal characteristics could reduce power by pre-processing. Can you tell me how the signal is modulated ?

Take a look at;
http://www.ti.com/lsds/ti/analog/dataconverters/data_converter.page
http://www.linear.com/products/Analog-to-Digital_Converters_(ADC)
http://www.linear.com/products/Comparators
 
anhnha said:
Hi,
I want to design an ADC with these specifications:
Fin = 20MHz
BW= 20MHz
ENOB > 4
Power consumption P < 1mW
Could anyone suggest me some ADC for this kind? I have searched a lot in
IEEE but there are only two ADC with SAR ADC and time-interleaved ADC.
The ultralow power consumption makes it hard for me to find a
architecture. I have little experience about this. Kindly help me.

By design an ADC do you mean design an IC? If so, you didn't look that hard in IEEE.

Harpe, P.J.A., Zhou, C., Bi, Y., Meijs, N.P. van der, Wang, X., Philips, K.J.P., Dolmans, G. & Groot, H. de (2011). A 26μ W 8 bit 10 MS/s asynchronous SAR ADC for low energy radios. IEEE Journal of Solid-State Circuits, 46(7), 1585-1595.

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05771068

Reduce the 8-bits to 4 and you can get the power no problem.

For a four-bit ADC though, maybe a straight flash is the way to go since you only need 15 comparators. Depends on the process you're using, of course.
 
This is slow but includes discussion of different methods including switched capacitors.
Very Low Power SAR ADC
 

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