Does Gate Oxide Breakdown Voltage Vary with Bias Polarity in NMOS Transistors?

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SUMMARY

The gate oxide breakdown voltage in NMOS transistors is significantly influenced by the bias polarity applied to the gate. According to the research by Hokari, Y in the paper "Stress voltage polarity dependence of thermally grown thin gate oxide wearout," published in IEEE Transactions on Electron Devices, vol. 35, no 8, August 1998, positive gate bias results in time-dependent dielectric breakdown (TDDB) lifetimes that are one order-of-magnitude longer compared to negative bias. Negative bias accelerates tunneling effects, leading to quicker breakdown. This establishes a clear relationship between bias polarity and gate oxide reliability.

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t2000_wong
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For a NMOS transistor, is there a difference in gate oxide breakdown voltage if we apply a positive bias on gate and a negative bias on gate? (assume S/D/bulk are ground)
 
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According to the paper
Hokari, Y, "Stress voltage polarity dependence of thermally grown thin gate oxide wearout" IEEE Transactions on Electron Devices, vol. 35, no 8, August 1998

there is a difference. In fact time-dependent dielectric breakdown lifetimes is one order-of-magnitude longer for positive biases and you get tunneling quicker with negative stress.
 

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