t2000_wong
- 1
- 0
For a NMOS transistor, is there a difference in gate oxide breakdown voltage if we apply a positive bias on gate and a negative bias on gate? (assume S/D/bulk are ground)
The gate oxide breakdown voltage in NMOS transistors is significantly influenced by the bias polarity applied to the gate. According to the research by Hokari, Y in the paper "Stress voltage polarity dependence of thermally grown thin gate oxide wearout," published in IEEE Transactions on Electron Devices, vol. 35, no 8, August 1998, positive gate bias results in time-dependent dielectric breakdown (TDDB) lifetimes that are one order-of-magnitude longer compared to negative bias. Negative bias accelerates tunneling effects, leading to quicker breakdown. This establishes a clear relationship between bias polarity and gate oxide reliability.
PREREQUISITESElectrical engineers, semiconductor device designers, and researchers focused on NMOS transistor reliability and gate oxide performance will benefit from this discussion.