A positive peak detector circuit

  • Thread starter FOIWATER
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  • #1
FOIWATER
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I am building a positive peak detector circuit using AD829 opamps.

I have attached my current circuit I built in multisim.

I used a "superdiode" configuration on the charging circuit so that I simultaneously get the charging across the capacitor, no discharging during the falling edge, and also no attenuation due to the diode.

The MOSFET is used to short the capacitor during the negative half cycle of the input wave. In this way, the positive peak detector is self resetting.

I used another AD829 set up to rail when the supply goes negative to gate the transistor and short the cap.

Well - it all works pretty good (See the attached waveforms) Except there are certain specifications this circuit has to be able to maintain, a voltage input of from 0.2V to 2.5V over a frequency range of 10Khz to 500Khz.

I have attached some pictures showing the input vs. output waveforms for different combinations of frequency and voltage

My main question is:
1)Why is the capacitor discharging on the falling edge? WHy is it not able to hold it's charge? The diode is in reverse bias. I even removed the mosfet from the circuit, it really cannot hold the charge but this only seems to be the case at low frequencies (It's reactance?)
2) Why is the ascension linear for high frequency and high voltage? (the linear charging path of the cap ie it does not follow the source) (Vcc is too low?)

I am having issues with the specs because it seems I need to change Vcc for certain configs whilst I need to change cap values for others.

I am having issues is there any theory that can be given to perhaps point me in the right direction?

ANY consideration appreciated.
 

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Answers and Replies

  • #2
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AD1 - clearly you have some leakage current (diode leaking, op amp input bias current) in the circuit or maybe oscop in multisim have some input resistance.

AD2 - This look like a typical slew rate limitation. The AD829 has a max Short-Circuit Current close to 32mA.
SR_max < 32mA/2nF = 16V/μs Try add emitter falower circuit at the AD829 output.
 
  • #3
FOIWATER
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Jony,

An emitter follower using a BJT, for current gain?
 
  • #5
FOIWATER
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Nice thanks friend,

I'll keep at it and post back..
 
  • #6
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I suspect you are not bringing the gate negative enough with respect to the source of the mosfet. Most likely it will need to be several volts negative depending on the particular mosfet you’re using.

In your second plot, it appears the capacitor value is decaying from 400 mV to 300 mV in 25 uS. For a 2 nF capacitor that means that the discharge resistance must be about 3600 ohms. The only place a value in that range could come from is the mosfet. You need to use a dual supply for your second opamp too and make sure the output goes negative.
 
  • #7
FOIWATER
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That's actually a NMOSFET in this program, I think you were assuming it's a PMOSFET?

I'll look into that as well Thanks Skeptic

PS: With the mosfet removed from the circuit, I receive the same droop
 
  • #8
meBigGuy
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Looks like leakage currents. Calculate the current required to produce the slope you see across a .002uF capacitor. Compare that to the specs for the 1N4148 and the amp.

Measure the currents, both through the diode and into the amplifier.

As an experiment, if you double the capacitor you will halve the long term droop.

There are other secondary effects you will need to consider if you want high accuracy, but first let's fully understand the droop caused by leakage. Notice how the droop increases as the reverse voltage across the diode increases.
 
  • #9
FOIWATER
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OK meBigGuy, yes I noticed that as well...

Jony - putting the emitter follower on the output offers great results at low frequencies, but removes the benifits previously obtained for high frequencies.

Not sure why it is doing that,

See attached Waveforms
 

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  • #10
FOIWATER
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Here's another circuit idea I got from a textbook,

But same story here.

The 0.2v/2.5v 10kHz-500kHz is killing me....

I don't even think it's possible at this point with this type or arrangement.

The capacitors are either too big to charge or too little to hold a charge and not droop.

The extremes of frequencies require one or the other..

See attatched

The idea is simply to add an extra opamp which brings the output voltage back to the anode of the second diode. Making the voltage across it zero volts and preventing leakage current (As mentioned by meBigGuy)

But, to no avail.
 

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  • #11
meBigGuy
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1. Your reset circuit is brutal. You need to short the capacitor without shorting the opamp output to ground.

2. .002 uF causes slew problems and you haven't fixed that. If you fix 1, you can make D1 a darlington. I'm not sure what issues you had with that previously.
 
  • #12
FOIWATER
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1. Your reset circuit is brutal. .

I'm trying here.

Adding the emitter follower to the output output (not grounding the opamp output) just complicated matters for me.
 
  • #13
meBigGuy
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I meant that if you fixed the reset circuit you could add the darlington. Otherwise shorting the darlington to ground would be extra brutal.

You still have the .002 slew rate problem, correct?
 
  • #15
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Can you post your simulation file?
 
  • #16
FOIWATER
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The multisim file?
Which results Jony
 
  • #17
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Yes, multisim schematics file.
 
  • #18
meBigGuy
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Do you still have the .002uF slew rate issue? How do you plan to address that?
Just post the same waveforms and schematic you posted initially (updated for the new circuit) and include the diode current when the reset occurs.

We can address the reset problem so we can address the slew rate problem.
 
  • #19
FOIWATER
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Yeah meBigGuy I still have that issue, I am unsure how to address it.
I did the calculation for my maximum slew rate required for this circuit with an input waveform of 2.5sin(2pift)
and I only got about 7V/us for the highest frequency (500kHz)
But the AD829 is good for up to 50v/us so obviously there is an issue with the circuit.
I can't post the multisim file here its an invalid file type..
The previous post is still about where I am at. I have tried adding resistor capacitor arrangement with the 0.002uf cap, and also tried tampering with the opamp hysteresis by adding capacitors to the other inputs of the AD829 but the range is still getting me.

About the reset circuit, I am unsure how to do it any other way,

About the output of the opamp being grounded, should I include a emitter follower?

About the AD829 being used as a comparator, should I replace it with a comparator?
 
  • #20
FOIWATER
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meBigGuy, do you have any suggestions for how I should monitor diode current during reset..
 
  • #21
meBigGuy
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meBigGuy, do you have any suggestions for how I should monitor diode current during reset..
I thought multisim would let you monitor currents. If not, you can insert a small resistor and measure the voltage across it.

I just thought of a problem with using an emitter follower, which is that when the input signal goes below the peak the opamp output goes to -5, and the peak voltage is on the emitter, back biasing it and possibly breaking it down. There are other ways to buffer the output, if that is what's needed.

As for the reset, we will see how much current is being drawn. You could put a series resistor in series with the discharge fet to limit the current. Or, you could disconnect it when you reset it (with a FET to ground that opens when you reset).

I see the slew of AD829 is 150V/us with a 500 ohm load , but short circuit current is only 32ma.

I think your slew rate is actually a bit higher than you calculated. The fast section of a sine wave is about 1/3 the period, so for a 500Khz that is 2uS/3 = ~700ns. 10V/700ns is 14V/uS.

14V/uS across .002uF (i = Cdv/dt) = .002uF*14V/uS = 28ma. I don't think the amp can drive its short circuit current actively (not sure) so it may be current limiting.

Try reducing the capacitor until the slew problem goes away. .001 might be low enough (just to test this theory).
 
  • #22
meBigGuy
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Have you looked at using an LF398? It has a slow acquisition time, but that may not be an issue in track and hold. You can use a comparator to stop sampling when the input drops below the output.
 
  • #23
FOIWATER
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You are right that reducing the capacitor solves the slew problem, however, it overcharges on the rising edge and picks up a positive peak detection which is inaccurate.

I will run a simulation and post back with the results you asked for tonight, I appreciate the help.
 
  • #24
meBigGuy
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The over charging may be due to the lag caused by the resistance of the diodes, or maybe an effect of the diode biasing amp. Not sure.
 
  • #25
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Attached is a circuit that could be a starting point. The circuit is not optimized and differs from yours in many ways. I'm sure it can be made simpler. However it does seem to work, at least with LTSPICE.

Included are the schematic, the netlist and a section of the plot. In the plot, the green trace is the 1 Vpk sinewave at 5 MHz and the blue trace is the peak voltage which is held for 0.1uS before it is reset. Despite its value of only 240pF, the capacitor's voltage doesn't seem to droop.
 

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  • #26
FOIWATER
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meBigGuy - I am starting to think it's the diode as well...

Skeptic, nice job.....

Personally I am trying to get this to work with the AD829, since as meBigGuy stated previously the circuit shouldn't really be out of the range of this device.

Skeptic, what kind of waveforms do you get for voltages between 20mV, to about 2.5 volts? how about frequencies between 10kHz and 500kHz?

These are the limits I have set for myself, Are they (in your opinion) attainable?
 
  • #27
FOIWATER
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I have added the BJT for current gain, it did not reduce the slew rate problem exactly,
I also replaced the AD829 with a LM311 comparator.
notice the pics attatched, the low voltage low frequency is still overcharging, while for high frequencies it is undercharging.

I also built this circuit and scoped it.

What a mess!
 

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  • #28
meBigGuy
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1. In the high frequency plot you can see that when the discharge FET turns off it dumps negative charge into the capacitor (through gate-drain junction).
The discharge FET comparator needs to be biased such that it can turn off slowly before the 0 crossing (or use a FET with less gate-drain capacitance). You need to slow down the switching signal. A way to test it is to add a capacitor on the output of the comparator to slow it down. Also, if you probe the gate and drain at the same time you will see the similarity.

2. The low frequency plot is trying to reach 5V, but it can't get there because there are 3 diode drops. Try only driving to 2.5V and see what it does. BTW, the same spike at the 0 crossover will be there in low frequency mode, but you just don't see it.



3. Replace the second diode with the emitter follower. 1 diode, 1 emitter follower (which is a diode).

4. The feedback *has* to go to the capacitor. That's a must. If the leakage is too much, then you have a problem and need to change to a cmos opamp. That in itself may be the reason an AD829 is not a good choice. But, if we can get the emitter follower to work you can increase the capacitor.
 
  • #29
FOIWATER
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OK I got rid of the 2nd diode, I see it isn't necessary not sure what I was thinking,

With the emitter follower I get some, weird waveforms lol

I will post in the AM. Thanks for the feedback.

What do you mean about the feedback having to go to the cap?
 
  • #30
meBigGuy
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The feedback to the input op-amp has to come from the storage cap not the base of the follower. The goal is for the voltage across the cap to equal the input voltage.

There is another approach to this that eliminates the reset FET. Look at the LF398. You need logic to determine when to sample though. Open the switch when the input drops below the output. Once the input crosses 0 you just close the switch.

As with any sample and hold you always have to deal with charge injection when you switch the FET (as you saw)
 

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