Engineering Drawing Circuits: Correctly Drawing NAND and NOR Gates with 2 Inputs

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The discussion focuses on the correct drawing of NAND and NOR gates with two inputs. The original poster clarifies a misunderstanding regarding the question, stating it pertains to single NAND and NOR gates rather than multiple gates. They seek confirmation on their circuit drawing and inquire about the output when all inputs are set to 1. There is a suggestion that the logic may require using the NOR of two NANDs, raising questions about equivalence. The conversation emphasizes the importance of accurately representing logic circuits for proper functionality.
MissP.25_5
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Hello.
Can someone check if I drew the circuit for (a) correctly? By the way, I translated the question wrong, it doesn't actually mean 2 NAND gates or 2 NOR gates, it just means NAND gates with 2 inputs and NOR gates with 2 inputs.
And how to do the second one?
 

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Check what your logic circuit itself will output with A=B=C=1

You seem to be saying I need the OR of two ANDs so I'll use the NOR of two NANDs. Maybe these are not equivalent?
 
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