Hello everyone, I have come across a question that I am having quite a hard time with. I am to draw a design of an SRAM chip with an organization of 2M*128 SRAM that uses 1K*1K arrays of D latches. And then the questions ends with saying, "if this design is not possible then explain why." I have looked at other SRAM designs and have noticed that the multiplication of their d latch arrays, the resulting number is large enough to cover the first number of the SRAM, in this case 2M. The other example I was looking at had a 32K*8 SRAM chip with 512*64 arrays of d latches. Assuming the array size is also in K, I multiplied 512 by 64 and came up with 32768. This covers the 32K of the SRAM chip. With my first example above, I multiplied 1K by 1K or 1000 * 1000 = 1000000. This does not cover the 2M of the SRAM chip. So am I to believe that it's not possible to design this chip? Also I could be totally wrong. I do not have that much experience in electrical engineering so forgive me. Any help at all would be greatly appreciated in helping me! Thank you.