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Homework Help: Help with VHDL to transition state diagram

  1. Mar 29, 2015 #1
    1. The problem statement, all variables and given/known data
    VHDL code:

    2. Relevant equations
    B2 = B7 * A1
    B3 = (B9 * B2) + (B1(1) * /B1(0) * /A1
    B6 = B9 + /A1
    B8 = B2 + (B9 * /A1) + (/B5 * (A1 + B7))
    If Clock = 1 and rising edge on A2 then we reset B4, B5, B7 to 0.
    B4 = B3 = (B9 * B2) + (B1(1) * /B1(0) * /A1
    B5 = B6 = B9 + /A1
    B7 = B8 = (B2 + (B9 * /A1) + (/B5 * (A1 + B7)))

    then this part is confusing me.

    end process;

    B1 <= B4 & B5 & B7; //What does this mean?
    B9 <= '1' when B4 = '0' and B5 = '1' else '0'; //B9 will equal 1 only if B4 and B5 is = to 1 else B9 = 0.
    with B1 select //Do not understand this part what does B1 select mean?
    A3 <=
    '0' when "000" | "111", //when what is 000 or 111?
    '1' when others;

    end architecture a1;

    3. The attempt at a solution
  2. jcsd
  3. Mar 29, 2015 #2


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    Gold Member

    Just to clarify, you need help converting this code to a state transistion diagram?

    Typically we need you to make an attempt first, but I will answer your direct questions.

    B4, B5, and B7 are defined as std_logic. So they are single bit elements
    B1 is defined as a 3 bit std_logic_vector.

    the & signal will result in a concatenation.


    c1 will be equal to "10"

    Almost, B4 has to be 0 and B5 has to be 1

    in spoken form, this mean A3 is equel to '0' when B1 is "000" or "111"
    for all other possible B1 values A3 is equal to '1'
  4. Mar 29, 2015 #3
    I made a table of truth, but I am not sure if this is correct.

    Are my middle signals need to each have a 0|1 bit ?
  5. Mar 30, 2015 #4


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    I'm not entirely sure what you are asking but you will need to fill in the truth table and make a state transition diagram.
    Also there is a LOT of unnecessary complications here. Is this a homework assignment? what is the purpose of the circuit?

    start by making a truth table for B2, B3, B6, and B8 using A1, B4, B5, and B7
    then make a separate truth table for A3 from B1 (you already did that)
    Last edited: Mar 30, 2015
  6. Mar 30, 2015 #5
    This is not really a home work just an optional practice I am doing to understand the concept more. I hate it when I cant understand a concept so I practice until I can master it :)

    I'm not entirely sure to understand.

    Could you just do the first line for the first table truth please, if this current one is not good?
    so the first 4 are my main input. in the middle my signals and last my output

    | B2 | B3 | B6 | B8 || B4 | B5 | B7 | B9 || A3 |

    thank you very much man for helping.
  7. Mar 30, 2015 #6


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    you essentially have 3 components to this circuit.

    concurrent logic, which has A1, B4, B5, and B7 as inputs,B2, and B9 as middle, and B3, B6, and B7as outputs.

    Then you have you memory holding section, which sets the value of B4, B5, and B7 on the rising edge of A2 based on the value of clock

    Then you have more concurrent logic which sets B1 and ultimately sets A3

    so first make a truth table for just B2 and B9 from A1, B4, B5, and B7. Then add 4 more columns for the others
  8. Mar 30, 2015 #7
    Why are B2 and B9 as middle?
    Also would each of my row have 4 bits too?
    also why do I have 3 inputs? when in my code it says «A3 : out std_logic);» In my understanding I have 1 output only?
  9. Mar 30, 2015 #8


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    it is a requirement to have a truth table for output of concurrent logic. I called B3, B6, and B7 outputs due to the fact that they are inputs to our memory device

    We do have memory in the system, specifically B4, B5, and B7. So we need to define the input to those stages. That input is defined by B3, B6, and B7 (and '0'). To make the truth table for those 3 signals we need to first find B2 and B9, hence 'middle' signals. Then the current state of B4, B5, and B7 along with A1 will be 'inputs'. When I said inputs, i only meant for your intermediate truth table.

    If you want to know how the output (A3) will change due to only A1, A2, and clock, then you will need a sequencing diagram and truth table. does that make sense? In addition your output will be unknown until you until you set B4, B5, and B7 to a known state
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