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How a cascaded common emitter transistor amplifier is modelled

  1. Sep 9, 2009 #1
    I want to learn how a cascaded common emitter transistor amplifier is modelled. I also want to know how all the calculations are done with regards to current and voltage gains, input and ouput impedances. I want to also know how we do the calculations with and without the emitter reistor. Can anyone kinkly come to my aid, I badly need help.
  2. jcsd
  3. Sep 9, 2009 #2

    The Electrician

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    Gold Member

    Can you show a schematic diagram of an actual circuit you would like to model?

    Is this a homework problem?
  4. Sep 9, 2009 #3


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    It is just like one stage, except you include the input impedance of the next stage, including any bias resistors, as part of the load for the first stage.

    Then you multiply the gains together to get the overall gain.

    But you don't need a computer to do it. You just use a calculator.
  5. Sep 17, 2009 #4
    Exactly. Just draw the equivalent circuit of the first stage , the second stage is connected to the first stage output and go on.

    As vk6kro said you can calculate the gains of each stage alone and then multiply the gains, or you can deal with the circuit as a whole circuit and determin the total gain (I think this is simpler to do).
  6. Sep 17, 2009 #5
    Is this ac or dc coupled? How many stages?
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