How Can I Design a 4-bit ALU with Integrated Memory for My Project?

[DiracBlue]

Homework Statement

In this lab, we are supposed to design and build a multi-page schematic for the operation of an 4-bit arithmetic logic unit (ALU) capable of performing addition (ADD), negation (NOT), and bitwise AND (using Mutlimedia Logic). You will then build a memory with four lines capable of storing four bits per line.

Homework Equations

I don't even understand how to start. I have a general idea of which gates to make/the circuitry for the addition, but as for the subtraction, 2-bit AND and even the layout of the ALU/memory I am completely lost. Any help would be amazing.

I know we need to use:
# Have two 4-bit inputs using two keypads
# Have one 4-bit output using a 7-segment displays
# Be capable of displaying both inputs using a 7-segment display for each input
# Capture the input in D-flip-flops (labeled "SR1" and "SR2" for source register)
# Have a clock button (labeled "CLK")
# Have a global reset to reset all registers and displays (labeled "Reset")
# Allow the user to input LC-3 opcodes using switches (see textbook), and store the opcode in an instruction register (labeled "IR")
# Display the operation in progress with LEDs or other output device
# Be capable of performing a bitwise AND of the two operands
# Be capable of performing a bitwise NOT of the first operand
# Be capable of performing an ADD of the two operands using a ripple-carry full adder
# Capture the result of the operation with D-flip-flops (labeled "DR")
# Display the result of the operation on a 7-segment display
# Display with an LED if the result of an ADD had a carry-out
# Display with an LED if the output of the ALU is zero (labeled "Z")
# Display with an LED if the output of the ALU is positive (labeled "P")
# Display with an LED if the output of the ALU is negative (labeled "N")

The Attempt at a Solution

I have the statement for the addition: f3=A, f2= A'(and)B + A(and)B', f1= B(and)C' + B'(and)C and f0= A'C'D + A'CD' + ABD' + AB'D

 

[berkeman]

Homework Statement

In this lab, we are supposed to design and build a multi-page schematic for the operation of an 4-bit arithmetic logic unit (ALU) capable of performing addition (ADD), negation (NOT), and bitwise AND (using Mutlimedia Logic). You will then build a memory with four lines capable of storing four bits per line.

Homework Equations

I don't even understand how to start. I have a general idea of which gates to make/the circuitry for the addition, but as for the subtraction, 2-bit AND and even the layout of the ALU/memory I am completely lost. Any help would be amazing.

I know we need to use:
# Have two 4-bit inputs using two keypads
# Have one 4-bit output using a 7-segment displays
# Be capable of displaying both inputs using a 7-segment display for each input
# Capture the input in D-flip-flops (labeled "SR1" and "SR2" for source register)
# Have a clock button (labeled "CLK")
# Have a global reset to reset all registers and displays (labeled "Reset")
# Allow the user to input LC-3 opcodes using switches (see textbook), and store the opcode in an instruction register (labeled "IR")
# Display the operation in progress with LEDs or other output device
# Be capable of performing a bitwise AND of the two operands
# Be capable of performing a bitwise NOT of the first operand
# Be capable of performing an ADD of the two operands using a ripple-carry full adder
# Capture the result of the operation with D-flip-flops (labeled "DR")
# Display the result of the operation on a 7-segment display
# Display with an LED if the result of an ADD had a carry-out
# Display with an LED if the output of the ALU is zero (labeled "Z")
# Display with an LED if the output of the ALU is positive (labeled "P")
# Display with an LED if the output of the ALU is negative (labeled "N")

The Attempt at a Solution

I have the statement for the addition: f3=A, f2= A'(and)B + A(and)B', f1= B(and)C' + B'(and)C and f0= A'C'D + A'CD' + ABD' + AB'D

Welcome to the PF.

That's a pretty big project. Start by drawing a block diagram, showing the data paths between the blocks, and what you initially think some of the control signals would be. Then you can go down into each block, and do logic diagrams for them. That's generally how you draw schematics anyway, in a hierarchical fashion, with the top page being the major blocks and the signals interconnecting them.