How can I design a sample and hold circuit to produce a desired waveform?

[syee10]

Sample and Hold Circuit Help!

Hi all,

I am designing a simple sample and hold circuit where the input is a sinusoidal analog input and it is control by a TTL compatible square wave (waveform A). The result waveform i should get is waveform B in the attach file but i tried a millions time i still can't get the same waveform. Someone there can help me out? I had attached all the file in the attachment..

 

[berkeman]

Hi all,

I am designing a simple sample and hold circuit where the input is a sinusoidal analog input and it is control by a TTL compatible square wave (waveform A). The result waveform i should get is waveform B in the attach file but i tried a millions time i still can't get the same waveform. Someone there can help me out? I had attached all the file in the attachment..

The gate drive for the FET looks wrong. Drive it high and low to sample and hold. Do not connect the gate to the input... ?

 

[syee10]

The gate is connected to a reference signal logic input. The analog input is connected to pin 5...

 

[berkeman]

The gate is connected to a reference signal logic input. The analog input is connected to pin 5...

Hmm. I guess I'm not understanding the connections. What is the purpose of R2? Why is there a "switch" in series with the gate? You don't ever want to float a gate...

 

[syee10]

I construct the circuit from the following reference..
http://mysite.du.edu/~etuttle/electron/elect25.htm

Is the circuit itself connected wrongly?

 

[berkeman]

I construct the circuit from the following reference..
http://mysite.du.edu/~etuttle/electron/elect25.htm

Is the circuit itself connected wrongly?

From your link:

For our purposes, we can command sample and hold by connecting a wire manually to -12 for HOLD, and leaving it disconnected for SAMPLE. For a practical circuit, we would make better arrangements for the control.

Emphasis added by me. And in your schematic implementation of the circuit in the link, the switch you have in the gate lead is misplaced. It should go from the bottom of R2 (which should be connected directly to the gate) to the -12V supply. The link implies that this simple switch can be used to force a HOLD (when closed), and allow the SAMPLE phase when open. The 1M resistor will limit the bandwidth of the sampling circuit to a few kHz, probably.

 

[syee10]

Thanks for your help =)